SSC TX output in idle state

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I'm trying to implement an I²C/SMBus master using SSC.

I can use SSC_CONL.PO to switch the clock idle from high (no transmission) to low (idle state between bytes).

I have to do something similar with the TX pin to generate the start and stop conditions. I haven't found any information on the TX pin idle state in the handbook.
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I finally followed up on this and checked Master TX pin with a voltmeter. Here are my results.

The SSC for SMBus/I²C is configured to shift on trailing clock edge and latch on leading edge, with high idle clock in half duplex mode. Under those conditions the Master TX pin is LOW in idle mode.

This makes it easy to produce the start/stop conditions. During SMBus communication all DAT edge changes are performed during CLK low. The only exceptions are the start and stop conditions, where a leading edge in DAT signals stop and a trailing ledge in DAT start.

The stop condition looks like this:

IDLE edge
____________________
CLK __/
________
DAT ______________/
STOP edge


The start condition looks like this:

______________Shift edge (start of transmisison)
CLK \_________

__
DAT \_____________________
START edge


These conditions can be met, simply by setting the DIR bit of the TX pin to 0 (configuration as input) between bus communications.
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