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Thread: Syncronizing a PWM to the EtherCAT distributed clock

  1. #1
    Beginner Beginner GraemeF is on a distinguished road
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    Syncronizing a PWM to the EtherCAT distributed clock

    Hi,

    I have an XMC4800 Auotmation Board V2 running an EtherCAT application controlling a thirdparty component via the eth port at a high data rate (125kHz). I'm using the PWM_CCU8 interrupt with a high priority to send the eth frames. I started and modified the ETHCAT_SSC_AUT_BASE_XMC48 example project.

    I have the PWM_CCU8_0 component set with:
    - PWM resolution [nsec]: 16
    - Frequency [Hz]: 125000
    - Channel 1 Duty Cycle [%]: 50

    I am synchronizing the PWM to the Distributed clock by setting the PWM_CCU8_0 Event 0 parameters to:
    - Function: External Start
    - Trigger edge: Rising
    And setting External Start to:
    - Function control: Clear And Start Timer

    I have also updated the EG_SYNC0 HW Signal Connections by adding a connection from iout to PWM_CCU8_0.ext_event0 so that the DC event will call both the SYNC0 handler and restart the PWM.


    1) So as far as I can tell, the PWM signal clear/restart gets synced to the SYNC0 interrupt but I would like to confirm this with an oscilliscope. I tried to use the ISOFACE outputs to monitor the events, but as I suspected they are too slow. Are there any general purpose IO pins that I can use to monitor these?

    I was thinking of using pin P4.3 which maps to pin 1 on the 6 pin user header, but I really need two pins (one for the sync0 event and another for the PWM event). Would it be possible to use the CAN TX/RX pins (P2.7 / P2.6)?


    2) The EtherCAT master DC cycle period seems to be slightly faster than the XMC PWM pulse train, so I'm only getting 124 interrups per millisecond rather than 125. And of course that will change depending on the system the XMC4800 is connnected to. Has anyone got any ideas on how I can adjust the PWM_CCU8 frequency to match the DC cycle period?


    Regards,
    Graeme.

  2. #2
    Beginner Beginner GraemeF is on a distinguished road
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    Hi,

    I decided that since I wasn't using any SPI components I would suck it and see, so I configured and connected to pins 4.3 (user header select) and 3.11 (user header DOut / MOSI). It looks like my PWM is resetting nicely at the SYNC0 DC event.

    I have changed the PWM_CCU8_0 event from "Period match" to "Compare 1 match while counting up" so that the event occurs 1/2 way through the PWM period rather than at the end and this helped stop the last IRQ being missed, but the last period is still short. So I'll still need to find a way to adjust the PWM frequency to match the DC cycle period.

    Regards,
    Graeme.

  3. #3
    Beginner Beginner GraemeF is on a distinguished road
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    After a bit of time checking with the oscilloscope (and checking EtherCAT register 0x92C, System Time Difference) it looks like the variance is in the 10's of nano seconds, so I probably don't need to worry about adjusting the PWM frequency.

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