CANGLOBAL [1.0.6] and CAN001 [1.0.6] Clock divider bug

Hi All,

There is a combination of parameters in the CANGLOBAL 1.0.6 and CAN001 1.0.6 GUIs that lead to the wrong baud rate being generated for the CAN Peripheral.

To reproduce on the latest DAVE3 and apps and chip definitions as of today 7Aug2013:

Create a new DAVE CE Project with XMC4500-F144x1024 as the target device

In the App Selection view, double click on CAN001 [1.0.6]

In the S/W App Connectivity View, Double click on CANGLOBAL/0 to bring up the CANGLOBAL/0 GUI. Enter the following parameters:



In the S/W App Connectivity View, Double click on CAN001/0 to bring up the CANGLOBAL GUI. Enter the following parameters:



We leave the CLK001/0 App GUI set at the default System Frequency of 120MHz.

Now generate code. Note that we have selected 60MHz CAN peripheral clock in the CANGLOBAL GUI.

Look at the code generated for Dave/Generated/src/CANGLOBAL/CANGLOBAL.c

/*  Function to Initialize CAN Clock registers
 */
void CANGLOBAL_Init(void)
{
  static uint8_t isInitialized = 0U;
  if(isInitialized == 0U)
  {
    /* Reset MultiCAN module */	
    RESET001_DeassertReset(PER1_MCAN0);
    /* Enable CAN Module */
    CAN->CLC &= (uint32_t)~CAN_CLC_DISR_Msk;
    /* Select the Divider Mode */
    while((CAN->CLC & CAN_CLC_DISS_Msk))
    {}
    CAN->FDR |= 1U <    /* Configure step value */
    CAN->FDR |= 1023U << CAN_FDR_STEP_Pos;
    isInitialized++;
  } 
}

Note that CAN_FDR.STEP is being loaded with 1023. We are using normal divider mode According to eqn. 18.1 in the XMC4500 reference manual:


This means that fcan becomes fpb * (1/(1024-1023)), which is just 1 * fpb. This gives fcan = 120MHz even though we asked for 60MHz.

Correct code generation should give CAN_FDR.STEP = 1022, so that fcan = fpb*(1/(1024/1022)) = fpb/2 = 60MHz.

I have verified this CAN bit timing on the oscilliscope, and I can clearly see the 2MB/s timing for FDR.STEP=1023 and
1MB/s timing for FDR.STEP=1022.
Here is a copy of the DAVE3 project showing this bug: