Aug 01, 2019
12:55 AM
- Mark as New
- Bookmark
- Subscribe
- Mute
- Subscribe to RSS Feed
- Permalink
- Report Inappropriate Content
Aug 01, 2019
12:55 AM
Hi,
Does each core have a separate RAM/Flash. Is there a hardware mechanism to prohibit other cores access this core RAM/Flash?
Make a list of which peripherals on hardware are public, which can be isolated by hardware mechanism and which can be isolated by software.
#8042000 12463
Does each core have a separate RAM/Flash. Is there a hardware mechanism to prohibit other cores access this core RAM/Flash?
Make a list of which peripherals on hardware are public, which can be isolated by hardware mechanism and which can be isolated by software.
#8042000 12463
- Tags:
- IFX
1 Reply
Aug 01, 2019
02:36 AM
- Mark as New
- Bookmark
- Subscribe
- Mute
- Subscribe to RSS Feed
- Permalink
- Report Inappropriate Content
Aug 01, 2019
02:36 AM
Hi,
Yes.
Aurix TC2xx doesn't have separate Flash, but software can still make Flash separated by software setting. Please see in the user manual chapter 5.12.6.6/5.12.6.7- Safety Memory Protection/Safety Register Protection
Aurix TC3xx,* Please see in the user manual chapter 5.4.6.1 Bus MPU
The Bus MPU comprises of:-
• Eight read and write protected regions of scratch pad memory (PSPR, DSPR) with enables for reads and writes on a per bus master basis.
• Eight read and write protected regions of DLMU with enables for reads and writes on a per bus master basis.
• Individual master read enables for accesses to the local PFlash Bank (LPB)
The protection scheme is based on the use of SRI tags to identify the master attempting the access and allows for
a six bit tag individually identifying up to 64 masters.
Each peripheral is public, can be isolated by by Hardware and can be isolated by Software.
NOTE: hardware mechanism, means other cores can’t access this core’s any resource even if modify some special registers, for example Register Access protection ACCEN1/0
Yes.
Aurix TC2xx doesn't have separate Flash, but software can still make Flash separated by software setting. Please see in the user manual chapter 5.12.6.6/5.12.6.7- Safety Memory Protection/Safety Register Protection
Aurix TC3xx,* Please see in the user manual chapter 5.4.6.1 Bus MPU
The Bus MPU comprises of:-
• Eight read and write protected regions of scratch pad memory (PSPR, DSPR) with enables for reads and writes on a per bus master basis.
• Eight read and write protected regions of DLMU with enables for reads and writes on a per bus master basis.
• Individual master read enables for accesses to the local PFlash Bank (LPB)
The protection scheme is based on the use of SRI tags to identify the master attempting the access and allows for
a six bit tag individually identifying up to 64 masters.
Each peripheral is public, can be isolated by by Hardware and can be isolated by Software.
NOTE: hardware mechanism, means other cores can’t access this core’s any resource even if modify some special registers, for example Register Access protection ACCEN1/0