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Thread: Constructing an H-Bridge With Output Bias

  1. #1
    New Member New Member ACST is on a distinguished road
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    Constructing an H-Bridge With Output Bias

    I have constructed an H-Bridge using two IR2101S driver ICs and four IRFZ44N power FETs, it works and there are no problems.

    I have now been given an additional requirement of bias voltages on the bridge output so, for example, I now supply a square wave that varies between 1.8V and Vsupply to the load.
    How can I do this? Should I supply a variable gate bias to two of the FETs (and risk destroying the driver ICs) or should I put bias resistors on the output and possibly alter the pulse shape?

    The circuit used is the standard one from the data sheet and the gate resistors are 22 ohms. Vsupply is 25V

    Regards

    Peter Gant
    Lab Technician
    ACST GmbH

  2. #2

    Infineon Employee
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    Hi Peter,

    so you need a positive square wave with a high level of 25V and a low level 1.8V?
    Would PWM with a low duty cycle be a possible solution in the low level state?
    The views expressed here are my personal opinions, have not been reviewed or authorized by Infineon and do not necessarily represent the views of Infineon.

  3. #3
    New Member New Member ACST is on a distinguished road
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    Output Bias?

    Sorry, no, I do not think that PWM would work in this application. I cannot go too far into details but the requirement is for an H-Bridge to supply fast pulses to a load in either direction with (ideally) nice sharp edges on the pulses.
    If I add a capacitor across the load so that I can do PWM this would destroy the pulse shape.

    So, is it possible to bias an H-Bridge into linear operation or are the power FETs only designed for on-off operation?

    Regards

    Peter Gant
    Lab Technician
    ACST GmbH

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