QSPI code for TC399

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User14049
Level 3
Level 3
Hi,

I am new in infineon controller, can any one provide me QSPI code for TC399 from basic level.

Calculation for time quantum to set SPI clock at 1Mhz(controller clock frequency is 20Mhz) and how to select ECON resistor using BACON resistor.

I want to configure QSPI5
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cwunder
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Sorry but I have to comment that you are asking a question without really giving enough information.
controller clock frequency is 20Mhz

Is this the crystal frequency? As usually the peripheral PLL is used (fPLL2) and typically this is either 200MHz or 160MHz. For 200MHz, to get a 1MHz SPI Clock you could use the following settings where Q=24, A=3,B=1 and C=3.

The ECON and BACON are configured to meet the device parameters required for communication.
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User14049
Level 3
Level 3
Hi,

20Mhz is crystal frequency.

Can you please write what calculation you have done for 200MHz to get Q=24, A=3,B=1 and C=3 or can you please share any doc.
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cwunder
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Enclosed is the formula from the user's manual (TQ=0, Q=24, A=3,B=1 and C=3, fPER=200MHz😞
3567.attach
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User14049
Level 3
Level 3
Hi,

How to select ISR for QSPI5.
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cwunder
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The interrupts all basically work the same and follow the common definition of the Service Request Control Register (SRC). You need to choose the SRPN that matches the entry in the vector table. This varies depending on the toolchain you are using. Then you need to select the TOS you want to use and also enable the interrupt both locally via the SRCi.SRE and globally enable interrupts via the PSW.IE.

As an example:

IFX_INTERRUPT(QSPI5_RxISR, 0, INTPRIO_CPU0_QSPI5_RX);
SRC_QSPI5RX.U = (CPU0_SERVICE << TOS) | (true << SRE) | INTPRIO_CPU0_QSPI5_RX;
IFX_INTERRUPT(QSPI5_TxISR, 0, INTPRIO_CPU0_QSPI5_TX);
SRC_QSPI5TX.U = (CPU0_SERVICE << TOS) | (true << SRE) | INTPRIO_CPU0_QSPI5_TX;
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User14049
Level 3
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Hi,

where will I find vector table?

If I am not wrong TOS will decide which CPU or DMA will provide service.
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cwunder
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The vector table is defined in the linker/locator file. You add the interrupt function in your source code such that the linker can add the location of your ISR in the table. The TOS indicates which CPU or the DMA should handle the interrupt.
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User14049
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HI,

sorry but I am not able to find out ISR table can you please elaborate little more
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cwunder
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To create an interrupt entry it usually involves two parts. You have to have a table defined in your linker/locator file and then you need to create the entry with a keyword or macro in a source file that the linker/locater can use.

What toolchain are you using?
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User14049
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HI,


I am using HI TECH compiler.
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cwunder
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Do you mean HighTec EDV-Systeme GmbH?

You open an example project that uses interrupts.

Basically you need to install the interrupt and then enable it. Here is a snippet that I did in the past for the STM.


/* the SRC0 Interrupt serviced by TriCore */
InterruptInstall(SRC_ID_STM0SR0, STM0_ISR0, INTPRIO_STM0_STMIR0, 0);
SRC_STM0SR0.U = CMP0_TOS | SRC_SRE | INTPRIO_STM0_STMIR0;



/**************************************************************************
Object: Interrupt routine for STM0_SR0
Parameters: arg
Return: Nothing
**************************************************************************/
void STM0_ISR0(int arg) {
(void)arg; /* dummy access for compiler warning */


/* load compare register for next event */
STM0_CMP0.U += CMP0_COMPARE_VALUE;
/* toggle LED which is connected to P13.1 */
P13_OMR.U = PORT_TGL_P1;
}

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User14049
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Level 3
IFX_INTERRUPT(ISR, VectabNum, prio)


from where I get VectabNum?

Suppose if it's for QSPI5, is there any calculation for it.
prio is from 0 to 255 and ISR I have to write.

Hear in my code VectabNum is zero for ADC and it's working, but I do't know how it's come.
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cwunder
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Hear in my code VectabNum is zero for ADC and it's working, but I do't know how it's come.

This means it is using the interrupt vector table for CPU0. On TC399 you can have 6 CPUs meaning you can have 6 interrupt vector tables.
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User14049
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Thanks cwunder,

Can I know how CUP0 can differentiate between ADC and QSPI5 interrupt.

Do it is define in Interrupt table vector if yes how can it get linked.
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User14049
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Level 3
cwunder wrote:
This means it is using the interrupt vector table for CPU0. On TC399 you can have 6 CPUs meaning you can have 6 interrupt vector tables.



Do you have any source file, which I can refer to create my own Interrupt vector table.
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