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  1. #1
    New Member New Member mjkinfhtx is on a distinguished road
    Join Date
    Mar 2019

    XMC4700 SPI TX FIFO via DMA doesn't load TBUF / Shift Register

    Hello All,

    I'm trying to setup an XMC4700, USIC.SSC slave (10MHz) to transmit via DMA to the USIC FIFO.

    The receive side is using RBUF via DMA and has no problems.

    The transmit side was previously using TBUF via DMA, but it was transmitting occasional 0xFF bytes, presumable because the Shift register was not being filled fast enough.

    The transmit side was then changed to DMA via the FIFO using the Fill Level mechanism to trigger the DMA.

    When I enable the DMA channel I can see the initial burst read of 8 bytes from the SRAM in the DMA channel registers (SAR and CTLH are as expected).

    When I trigger the initial Service Request I can see that the DMA has burst transferred the 8 bytes into the FIFO (TBFLVL == 8) and the burst transferred another 8 bytes from the SRAM.

    When I then enable the SPI channel and start my external SPI Master, the SPI slave transmits an 0xFF byte, followed by the contents of the FIFO. My data is always shifted by 1 byte and the last byte is wrapped to the next transmission.

    I was expecting the initial FIFO fill level to be less than 8, as the transfer to the FIFO should have also loaded the TBUF / DSU with the first byte for transmission.

    So, now the question:

    As an XMC4700 SPI slave, how do I trigger the initial SPI load to TBUF / DSU from the data already loaded in the FIFO?

  2. #2

    Infineon Employee
    Infineon Employee
    jferreira will become famous soon enough
    Join Date
    Oct 2012

    See attached example.The master clock is generated by a CCU slice and the CS by a GPIO.
    Click image for larger version

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    The views expressed here are my personal opinions, have not been reviewed or authorized by Infineon and do not necessarily represent the views of Infineon.

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