Mar 05, 2019
06:26 AM
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Mar 05, 2019
06:26 AM
Hi
We have problem that VDDP or VDDC error handling.
In usermanual, start->active(if detectet vddp or vddc over voltage/overload)->start and error supp++
-> if err supp=5-> sleep
Our situation is this, and it is not recover by power on reset.
It is only recover by re programming.
How we can handling VDDP/VDDC over voltae or over load error?
Is there need clear these flag? We arenot using these interrupt.
Would you check this one?
Thanks
We have problem that VDDP or VDDC error handling.
In usermanual, start->active(if detectet vddp or vddc over voltage/overload)->start and error supp++
-> if err supp=5-> sleep
Our situation is this, and it is not recover by power on reset.
It is only recover by re programming.
How we can handling VDDP/VDDC over voltae or over load error?
Is there need clear these flag? We arenot using these interrupt.
Would you check this one?
Thanks
- Tags:
- IFX
6 Replies
Mar 07, 2019
12:20 AM
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Mar 07, 2019
12:20 AM
Hi Justin,
Did you try to run your program in debug mode ? Do you have the same behaviour ?
Best Regards
Did you try to run your program in debug mode ? Do you have the same behaviour ?
Best Regards
Mar 07, 2019
12:49 AM
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Mar 07, 2019
12:49 AM
Hi
I didn’t try the debugger. Cause this issue is occur at temperature chamber.
So we did programming for debug mode, it is good work.
And I have same experience.(it is second time)
I think fail flag(VDDP/VDDC over load or over voltage) does not cleared by POR some situation.
So do we need clear these flag at initial routine??
Thanks
I didn’t try the debugger. Cause this issue is occur at temperature chamber.
So we did programming for debug mode, it is good work.
And I have same experience.(it is second time)
I think fail flag(VDDP/VDDC over load or over voltage) does not cleared by POR some situation.
So do we need clear these flag at initial routine??
Thanks
Mar 09, 2019
12:36 PM
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Mar 09, 2019
12:36 PM
Hi,
are you in an undervoltage scenario? I.e.: VS < 8V.
Please give us more information in order to help us reproducing your case.
Do you have an scope shot of VDDP/VDDC?
Best regards
are you in an undervoltage scenario? I.e.: VS < 8V.
Please give us more information in order to help us reproducing your case.
Do you have an scope shot of VDDP/VDDC?
Best regards
Mar 10, 2019
07:15 PM
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Mar 10, 2019
07:15 PM
Hi
1. Under voltage scenario
- We check about 7V via ADC2 Channel of VS, and if it is under 7V, reset by "WDT_STOP()" at every initial routine.
2. Reset port has decoupling capacitor that it 100nF.(I think it is pretty big value)
3.we can not scope short VDDP/VDDC but when we check this output voltage value, these value range is the good range.
4.Our testing condition is below here.
- 0~8V increment by 10sec.
- 8~0V decrement by 10sec
- 0~4V increment by 5sec
- 4~0V decrement by 5sec.
this is one cycle.
Thanks.
1. Under voltage scenario
- We check about 7V via ADC2 Channel of VS, and if it is under 7V, reset by "WDT_STOP()" at every initial routine.
2. Reset port has decoupling capacitor that it 100nF.(I think it is pretty big value)
3.we can not scope short VDDP/VDDC but when we check this output voltage value, these value range is the good range.
4.Our testing condition is below here.
- 0~8V increment by 10sec.
- 8~0V decrement by 10sec
- 0~4V increment by 5sec
- 4~0V decrement by 5sec.
this is one cycle.
Thanks.
Mar 17, 2019
02:09 PM
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Mar 17, 2019
02:09 PM
ok, understood.
The POR should clear all flags. In case of VS = 12V everything works as expected?
Without scope plots debugging is tricky 😉
The POR should clear all flags. In case of VS = 12V everything works as expected?
Without scope plots debugging is tricky 😉
Mar 17, 2019
11:55 PM
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Mar 17, 2019
11:55 PM
Hi
Yes it should be cleared.
Now it was good work.
Thanks for your support.
Yes it should be cleared.
Now it was good work.
Thanks for your support.