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Thread: [XMC4700] Cannot SPI(Fullbuplex) Master Received Correctly Data

  1. #1
    New Member New Member OnionOnion is on a distinguished road
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    [XMC4700] Cannot SPI(Fullbuplex) Master Received Correctly Data

    Hi All experts,

    I trying to SPI (full duplex) communication on XMC4700 Relax kit based on Example project for XMC4500. but It doesn't works. Master transmit data is correct, Master received data is incorrect. incorrect means a not expected data from Slave ch.
    Master asigned to USIC2 0ch, Slave asigned to USIC1 ch0, on the XMC4700 Relax kit. I have worring that maybe setting is wrong for Master and Slave or run out of a settings for Master and Slave.
    please advice.
    *I use the Example project is "SPI_SLAVE_EXAMPLE_XMC4500.zip"

    Please refer attached files.
    Check_data_buffer.png...it shows master and slave received buffer.
    Master_Setting.png...it shows SPI_MASTER DAVE App setting.
    Slave_Setting.png...it shows SPI_SLAVE DAVE App setting.
    Click image for larger version

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    Click image for larger version

Name:	Master_Setting.png
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    ?????? ?????? Slave_Setting.png‎  
    Last edited by OnionOnion; Feb 28th, 2019 at 01:57 AM.

  2. #2
    New Member New Member OnionOnion is on a distinguished road
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    update for this issue

    I inform you that clarified a problem by debug. the issue happen when 24MHz baud-rate situation. it does not depends on data length.
    Problem is clock does not fallen to Low level. please give me a advice for solving this problem.
    Then I attached few files. please refer the files.

    Cap_24MHz CLK.png...captured 24MHz baud-rate on the oscilloscope.
    XMC4700_SPI_DMA_0306.zip...this project.
    ?????? ?????? Cap_24MHz CLK.png‎  
    ?????

  3. #3

    Infineon Employee
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    jferreira will become famous soon enough
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    Hi,

    Find attached the fixed project:
    1. Upgraded to latest XMCLib and DAVE APPs version
    2. DMA interrupt of SLAVE is set to highest
    3. Disable Enable Inverted clock input and Enable immediate transmission of first bit in SLAVE configuration
    4. Enabled delay compensation for master.

    Regards,
    Jesus
    ?????
    The views expressed here are my personal opinions, have not been reviewed or authorized by Infineon and do not necessarily represent the views of Infineon.

  4. #4
    New Member New Member OnionOnion is on a distinguished road
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    Hi Jesus,

    Thanks for your advice.
    I had confirmed your attachment project on my XMC4700 / XMC4800 Relax Kit Series-V1. it works can receive and transfer Interrupt and reception data(10 bytes) on the SLAVE. But it doesn't work the receive and transfer Interrupt, and reception data(10 bytes) on the MASTER side.
    The contents of 1-4 is already set in your attachment project?
    Also, do I need to set other contents?

  5. #5
    New Member New Member OnionOnion is on a distinguished road
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    [QUOTE=OnionOnion;18945]Hi Jesus,

    I tried your sample code but master clock from XMC still not working correctly. It doesn't work as completely falling clock line. I think that clock line issues are important.
    Could you please give me a your idea or advice, why master clock does not reach to low-level?

    I checked following items on your code and confirmed it is working correctly.
    1-1. SPI Master transmit data to SPI Slave.
    1-2. Slave receive interrupt did work.
    1-3. Master transmit data and Slave received data are completely same. Please refer to "master_send_data_slave_rec_data.png"

    Your project didn't work at followings below:
    2-1. Slave transmit data to Master did not work.
    Master output did not work, It means the SCLK always kept low-level, CS signal always kept high-level.
    Master receive interrupt did not work.
    2-2. Master did not receive data from Slave. I checked on the DAVE Expressions window, please refer to "slave_rec_data_master_rec_data.png".

    I have some questions about your modification contents.
    1. Upgraded to latest XMCLib and DAVE APPs version
    I used API version is followings
    - SPI_MASTER : v4.3.24
    - SPI_SLAVE : v4.0.8
    - GLOBAL_DMA : v4.0.8
    - CPU_CTRL_XMC4 : v4.0.16
    - CLOCK_XMC4 : v4.0.22
    - DGITAL_IO : v4.0.16
    Could you please check above contents is last version?

    2. DMA interrupt of SLAVE is set to highest
    I can’t change the Interrupt priority of SPI_SLAVE at SPI_SLAVE DAVE App. Please refer to "SPI_SLAVE_INT_Setting.png".
    DMA interrupt priority setting as "DMA_Setting.png". Is it correct?

    3. Disable Enable Inverted clock input and Enable immediate transmission of first bit in SLAVE configuration
    I confirmed this setting was done in your project.

    4. Enabled delay compensation for master.
    I cannot understand how to set this.
    Please refer to "SPI_MASTER_DELAY_SETTING.png". It shows current settings on SPI_MASTER DAVE App. Is it correct?

    And I would like to know about how to set internal loop-back mode.
    Because I would like to check master clock issue without IO drive strength.
    ?????? ?????? DMA_Setting.png‎   master_send_data_slave_rec_data.png‎   slave_rec_data_master_rec_data.png‎   SPI_MASTER_DELAY_SETTING.PNG‎   SPI_SLAVE_INT_Setting.png‎  

    Last edited by OnionOnion; Apr 1st, 2019 at 11:09 PM.

  6. #6
    New Member New Member OnionOnion is on a distinguished road
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    Hi Jesus,
    Thank you for advice.
    I changed A1+ to A2 pad on SPI, the problem improves now. And I try internal loop-back to clarify this problem that depend on drive capability.

  7. #7
    New Member New Member OnionOnion is on a distinguished road
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    Hi Jesus,
    I'm trying Internal loop-back mode on DAVE4 (I use XMC4700 relax kit). but I don't know how to set up the internal loop-back mode.
    How do i set up on DAVE4 for the Internal loop-back setting?

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