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Thread: [XMC4700] Cannot SPI(Fullbuplex) Master Received Correctly Data

  1. #1
    Beginner Beginner OnionOnion is on a distinguished road
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    [XMC4700] Cannot SPI(Fullbuplex) Master Received Correctly Data

    Hi All experts,

    I trying to SPI (full duplex) communication on XMC4700 Relax kit based on Example project for XMC4500. but It doesn't works. Master transmit data is correct, Master received data is incorrect. incorrect means a not expected data from Slave ch.
    Master asigned to USIC2 0ch, Slave asigned to USIC1 ch0, on the XMC4700 Relax kit. I have worring that maybe setting is wrong for Master and Slave or run out of a settings for Master and Slave.
    please advice.
    *I use the Example project is "SPI_SLAVE_EXAMPLE_XMC4500.zip"

    Please refer attached files.
    Check_data_buffer.png...it shows master and slave received buffer.
    Master_Setting.png...it shows SPI_MASTER DAVE App setting.
    Slave_Setting.png...it shows SPI_SLAVE DAVE App setting.
    Click image for larger version

Name:	Check_data_buffer.png
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    Click image for larger version

Name:	Master_Setting.png
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    ?????? ?????? Slave_Setting.png‎  
    Last edited by OnionOnion; Feb 28th, 2019 at 01:57 AM.

  2. #2
    Beginner Beginner OnionOnion is on a distinguished road
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    update for this issue

    I inform you that clarified a problem by debug. the issue happen when 24MHz baud-rate situation. it does not depends on data length.
    Problem is clock does not fallen to Low level. please give me a advice for solving this problem.
    Then I attached few files. please refer the files.

    Cap_24MHz CLK.png...captured 24MHz baud-rate on the oscilloscope.
    XMC4700_SPI_DMA_0306.zip...this project.
    ?????? ?????? Cap_24MHz CLK.png‎  
    ?????

  3. #3

    Infineon Employee
    Infineon Employee
    jferreira will become famous soon enough
    Join Date
    Oct 2012
    Posts
    509
    Hi,

    Find attached the fixed project:
    1. Upgraded to latest XMCLib and DAVE APPs version
    2. DMA interrupt of SLAVE is set to highest
    3. Disable Enable Inverted clock input and Enable immediate transmission of first bit in SLAVE configuration
    4. Enabled delay compensation for master.

    Regards,
    Jesus
    ?????
    The views expressed here are my personal opinions, have not been reviewed or authorized by Infineon and do not necessarily represent the views of Infineon.

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