DMA to transfer data to EBU

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Qu19_4750531
Level 2
Level 2
Hi Infineon Team,

I need your support to figure out issue i am facing to establish DMA transfer from RAM buffer to EBU region.

I am trying to transmit stream of data byte from RAM to EBU region 0x60000000.

i am using below configuration-
#define EBU_BASE_ADDRESS 0x60000000U

XMC_DMA_CH_CONFIG_t dma_ch_config =
{
.block_size = 2048,
//.src_addr = (uint32_t)&source_data[0],
//.dst_addr = ( uint32_t)EBU_BASE_ADDRESS,
.src_transfer_width = XMC_DMA_CH_TRANSFER_WIDTH_16,
.dst_transfer_width = XMC_DMA_CH_TRANSFER_WIDTH_16,
.src_address_count_mode = XMC_DMA_CH_ADDRESS_COUNT_MODE_INCREMENT,
.dst_address_count_mode = XMC_DMA_CH_ADDRESS_COUNT_MODE_NO_CHANGE,
.src_burst_length = XMC_DMA_CH_BURST_LENGTH_8,
.dst_burst_length = XMC_DMA_CH_BURST_LENGTH_8,
.transfer_flow = XMC_DMA_CH_TRANSFER_FLOW_M2M_DMA,
.transfer_type = XMC_DMA_CH_TRANSFER_TYPE_SINGLE_BLOCK,
.enable_interrupt = true
};

XMC_DMA_Init(XMC_DMA0);
XMC_DMA_CH_Init(XMC_DMA0, 0, &dma_ch_config);
XMC_DMA_CH_EnableEvent(XMC_DMA0, 0, XMC_DMA_CH_EVENT_BLOCK_TRANSFER_COMPLETE);

/* Enable DMA event handling */
NVIC_SetPriority(GPDMA0_0_IRQn, 11);
NVIC_EnableIRQ(GPDMA0_0_IRQn);

and in code when i am ready to transmit data, i call below function-
XMC_DMA_CH_Enable(XMC_DMA0, 0);

I have also written ISR where i clear the event status
void GPDMA0_0_IRQHandler(void)
{
XMC_DMA_CH_ClearEventStatus(XMC_DMA0, 0, XMC_DMA_CH_EVENT_BLOCK_TRANSFER_COMPLETE);
}

Is there anything i missed in above DMA configuration ? When i run above code, system crashes immediately after i enabled DMA channel and it didnt go to ISR( in stack call i see code crashes due to Bus Handler / MemManage handler).
However, when i changed destination address to some intermediate buffer address rather than EBU region 0 address, it works well i.e. i see code breaks in ISR and also i see destination buffer value gets updated with respect to source buffer.

Is there anything specific i need to take care while transmitting data to EBU via DMA ? I also modified flow control to M2P instead of M2M, but no luck.
is it possible to transmit chunk of data from memory i.e. RAM buffer to EBU region 0 location ?

Any help in this regard is much appreciated.

Regards,
Query1920
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3 Replies
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jferreira
Employee
Employee
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Hi,

How does your EBU configuration look like?
See attached example of using DMA to transfer data to EBU region used to interface an SDRAM.

Regards,
Jesus
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Qu19_4750531
Level 2
Level 2
I am using EBU in Async mode to transfer data to NAND flash.
My EBU configuration is almost same as the example you shared except the burst length sync, burst flash clock feedback.

Below is my configuration-


// Zero the configuration structure before we set anything.
configuration.ebu_clk_config.raw0 = 0U;
configuration.ebu_mode_config.raw0 = 0U;
configuration.ebu_free_pins_to_gpio.raw0 = 0U;

// These values get written to the CLC register.
configuration.ebu_clk_config.ebu_clk_mode = 1U; //Fcpu is selected
configuration.ebu_clk_config.ebu_div2_clk_mode = 0U; //standard clocking mode selected
configuration.ebu_clk_config.ebu_clock_divide_ratio = 3U; //Divide by 4 ; Asynchronous cycle Fcpu/4 is used and Febu is not being used

// These values get written to the MODCON register.
configuration.ebu_mode_config.ebu_sdram_tristate = 1U;
configuration.ebu_mode_config.ebu_extlock = 1U;
configuration.ebu_mode_config.ebu_arbsync = 0U;
configuration.ebu_mode_config.ebu_arbitration_mode = 3U; // Master mode.
configuration.ebu_mode_config.bus_timeout_control = 0U;
configuration.ebu_mode_config.ebu_ale_mode = 0U;

// These values get written to the USERCON register.
configuration.ebu_free_pins_to_gpio.address_pins_gpio = 0x1FFU;
configuration.ebu_free_pins_to_gpio.adv_pin_gpio = 0U;

Is there any specific configuration in EBU i need to take care of for DMA transfer ?
Also, my EBU is running at different clock as compared to DMA. Can this be an issue?
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Qu19_4750531
Level 2
Level 2
Also another question, can i transfer 2084 bytes of data to just one location of EBU i.e. base address of region 0 0x60000000 by having below configuration in DMA
.src_address_count_mode = XMC_DMA_CH_ADDRESS_COUNT_MODE_INCREMENT,
.dst_address_count_mode = XMC_DMA_CH_ADDRESS_COUNT_MODE_NO_CHANGE,
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