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Thread: Memory parity error xmc4400

  1. #1
    New Member New Member rum will become famous soon enough
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    Memory parity error xmc4400

    Dear support,

    I trying to use memory parity check feature. Configuration is pretty straightforward and simple using PEEN, PETE, PERSTEN, TRAPDIS.
    Trap is enabled only for peripheral memories. My problem is that I get bus error immediately at start. Error address points to DSRAM_2_comm memory.
    When I exclude this memory from PEEN, program executes correctly.
    I have not tested parity fault injection yet.

    anybody seen such problem?

    rum

  2. #2
    New Member New Member rum will become famous soon enough
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    Small update. In DSRAM2 memory I have declared "noinit" section. This is to carry some state information in case I need to execute sw. reset.
    Now, after parity checks have been enabled and if I read first time this state from DSRAM2 bus fault is generated.
    Manual states that parity bits are stored with every write to RAM and checked at read access. In my case, last write was before sw. reset.

    Any answer from Infineon would be appreciated

    rum

  3. #3

    Infineon Employee
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    Hi,

    I cannot reproduce your issue. The parity logic generates additional parity bits which are stored along with each data word at a write operation. A read operation implies checking of the previous stored parity information. The parity bits are "resistant" to the SW reset.
    See attached file.

    Regards,
    Jesus
    ?????
    The views expressed here are my personal opinions, have not been reviewed or authorized by Infineon and do not necessarily represent the views of Infineon.

  4. #4
    New Member New Member rum will become famous soon enough
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    Hi Jesus,

    thanks for your answer. In the meanwhile I have moved ahead already. It seems that parity check can be enabled only after the peripheral has been initialized. Now I am enabling all parity checks after all peripherals are initialized.
    I am now developing part to test correct operation of parity checks (according to errata sheet).
    For DSRAM1+2 works well. For PSRAM I am not getting bus fault but hard fault, debugger is not stopping properly on __bkpt instruction. Somehow it gets lost.

    For peripheral memories it does not work at all. I was expecting NMI but never occurs.
    I use following code fragment for example:

    case 3: // test USIC0
    SCU_PARITY->MCHKCON = SCU_PARITY_MCHKCON_USIC0DRA_Msk;
    SCU_PARITY->PMTSR = SCU_PARITY_PMTSR_MTEU0_Msk;
    SCU_PARITY->PMTPR = (((uint32_t)1 << SCU_PARITY_PMTPR_PWR_Pos) & SCU_PARITY_PMTPR_PWR_Msk); //odd parity
    ptr = (uint32_t*)(&(USIC0_CH0->TBUF[31]));
    *ptr = 0; // even parity
    trapread = *ptr; // at this read, nmi should occur

    optimization is set to 0, I verified each instruction is executed.
    any suggestion what is wrong? can you advice which memory area should be accessed for each peripheral? For example ETHTX and RX, or for PMU?
    application note would be really helpful.

    rum

  5. #5
    New Member New Member rum will become famous soon enough
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    my code

    case 4: // test USIC1
    // disable watchdog
    //WDT_DISABLE();
    // enable testing USIC1
    SCU_PARITY->MCHKCON = SCU_PARITY_MCHKCON_USIC1DRA_Msk;
    SCU_PARITY->PMTSR = SCU_PARITY_PMTSR_MTEU1_Msk;
    // odd parity
    SCU_PARITY->PMTPR = (((uint32_t)1 << SCU_PARITY_PMTPR_PWR_Pos) & SCU_PARITY_PMTPR_PWR_Msk);
    USIC1_CH0->IN[31] = 0;
    trapread = USIC1_CH0->IN[31];
    break;

    if WATCHDOG disable is commented out as above, program resets due to watchdog, if WATCHDOG disable is present in the code, it hangs at last read instruction. Debugger cannot stop execution anymore. Need to exit and restart.

    NO NMI triggering. Why?

    any useful hint from Infineon support?

    thanks

    rum

  6. #6
    New Member New Member rum will become famous soon enough
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    update:

    for PSRAM test I made it work. manual states:

    Parity error signaling with trap generation is not recommended
    to be used for memories capable of bus error generation and therefore should be
    disabled.

    in my case it was never working, processor gets lost somewhere, debugger stop not working, fortunately if watchdog is used reset is generated. Bus fault never occurs for PSRAM parity test.

    If however NMI trap is used to detect parity error on PSRAM then xmc4400 behaves correctly and NMI is triggered.

    can Infineon advice memory location to test for PMUprefetch and ETH TX&RX ?

    rum

  7. #7

    Infineon Employee
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    Quote Originally Posted by rum View Post
    NO NMI triggering. Why?
    rum
    Did you enable the trap at SCU_TRAP->TRAPDIS &= (uint32_t)~SCU_TRAP_TRAPSTAT_PET_Msk;
    The views expressed here are my personal opinions, have not been reviewed or authorized by Infineon and do not necessarily represent the views of Infineon.

  8. #8
    New Member New Member rum will become famous soon enough
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    As said above manual does not recommend to enable trap on memory capable of generating bus fault, PSRAM is that memory. But it does not work as described above. If trap is enabled for PSRAM then NMI is generated, that is working!

    Now I have identified another problem.

    If parity error is enabled on USB memory then immediately when I plug in USB cable to my board, TRAP is generated with PEUSB bit set in PEFLAG register.
    If parity check on USB is not enabled then my USB is working fine.

    There is no functional deviation in errata that parity check does not work for USB memory.

    rum

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