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Thread: Memory parity error xmc4400

  1. #1
    Intermediate Intermediate rum will become famous soon enough
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    Memory parity error xmc4400

    Dear support,

    I trying to use memory parity check feature. Configuration is pretty straightforward and simple using PEEN, PETE, PERSTEN, TRAPDIS.
    Trap is enabled only for peripheral memories. My problem is that I get bus error immediately at start. Error address points to DSRAM_2_comm memory.
    When I exclude this memory from PEEN, program executes correctly.
    I have not tested parity fault injection yet.

    anybody seen such problem?

    rum

  2. #2
    Intermediate Intermediate rum will become famous soon enough
    Join Date
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    280.3125
    Small update. In DSRAM2 memory I have declared "noinit" section. This is to carry some state information in case I need to execute sw. reset.
    Now, after parity checks have been enabled and if I read first time this state from DSRAM2 bus fault is generated.
    Manual states that parity bits are stored with every write to RAM and checked at read access. In my case, last write was before sw. reset.

    Any answer from Infineon would be appreciated

    rum

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