Feb 06, 2019
01:27 PM
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Feb 06, 2019
01:27 PM
Hello,
after I change the TIM0 -Register. it stopps Why the serial interface is pending?
SCU_GENERAL->PASSWD = 0x000000C0UL;
SCU_CLK->CLKCR = 0x3FF10100; // Config SCU Clock = 32MHz , PCLK = 64 MHz
while((SCU_CLK->CLKCR)&0x40000000UL); // wait for VDDC to stabilize
SCU_GENERAL->PASSWD = 0x000000C3UL;
SCU_GENERAL->PASSWD = 0x000000C0UL;
SCU_CLK->CGATCLR0 |= SCU_CLK_CGATCLR0_RTC_Msk; //disable gating
while((SCU_CLK->CLKCR)&0x40000000UL); // wait for VDDC to stabilize
SCU_GENERAL->PASSWD = 0x000000C3UL;
SCU_CLK->CGATSET0 |= 0xfff; // Modul Clock enable , all Modul's
while(SCU_GENERAL->MIRRSTS != 0) { }
RTC->TIM0=temp;
while(SCU_GENERAL->MIRRSTS != 0) { } //here it stops
RTC->TIM1=0;
RTC->CTR |=RTC_CTR_ENB_Msk;
after I change the TIM0 -Register. it stopps Why the serial interface is pending?
SCU_GENERAL->PASSWD = 0x000000C0UL;
SCU_CLK->CLKCR = 0x3FF10100; // Config SCU Clock = 32MHz , PCLK = 64 MHz
while((SCU_CLK->CLKCR)&0x40000000UL); // wait for VDDC to stabilize
SCU_GENERAL->PASSWD = 0x000000C3UL;
SCU_GENERAL->PASSWD = 0x000000C0UL;
SCU_CLK->CGATCLR0 |= SCU_CLK_CGATCLR0_RTC_Msk; //disable gating
while((SCU_CLK->CLKCR)&0x40000000UL); // wait for VDDC to stabilize
SCU_GENERAL->PASSWD = 0x000000C3UL;
SCU_CLK->CGATSET0 |= 0xfff; // Modul Clock enable , all Modul's
while(SCU_GENERAL->MIRRSTS != 0) { }
RTC->TIM0=temp;
while(SCU_GENERAL->MIRRSTS != 0) { } //here it stops
RTC->TIM1=0;
RTC->CTR |=RTC_CTR_ENB_Msk;
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