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Thread: PLL Frequency Maximum? --> Datasheet vs. system_XMC4700.c

  1. #1
    Beginner Beginner EbbeSand is on a distinguished road
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    PLL Frequency Maximum? --> Datasheet vs. system_XMC4700.c

    Hello forum members and all of you first a nice St. Nicholas day.

    The below command is out from the above mentioned c-file

    Code:
    /*******************************************************************************
     * Default clock initialization
     * fPLL = 288MHz => fSYS = 144MHz => fCPU = 144MHz
     *                                => fPB  = 144MHz
     *                                => fCCU = 144MHz
     *                                => fETH = 72MHz
     *               => fUSB = 48MHz
     *               => fEBU = 72MHz
     *
     * fUSBPLL Disabled, only enabled if SCU_CLK_USBCLKCR_USBSEL_USBPLL is selected
     *
     * fOFI = 24MHz => fWDT = 24MHz
     *******************************************************************************/
    In the demo from Infineon the PLL Setup was realized with the Parameter


    Code:
    #elif OSCHP_FREQUENCY == 12000000U
    #define PLL_PDIV (1U)
    #define PLL_NDIV (47U)
    #define PLL_K2DIV (0U)
    If I made the calculation I also get the 288 MHz for the PLL frequency

    But in the Manual XMC4000 Family V1.0 2016-01 in the Cappter 3.3.4 Phase Locked Loop (PLL) Characteristics

    The MAX. PLL base frequency is 140 MHz is this OK, in my opinion no.

    But also in the DAVE app and in the examples you can set this frequency or I miss something

    Thanks for your Help

    With best regards

    EbbeSand

  2. #2
    Beginner Beginner EbbeSand is on a distinguished road
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    Possibly written too complicated

    In the Manual the Maximum base PLL fequency is 140 MHz. (see Picture)

    Click image for larger version

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    Why then, in most examples, are PLL operated at 288 or 144 MHz?

    Table 11-5 (see Picture below) in the reference manual indicate the possible
    dividers for the different clocks. There is always mentionted of 144 MHz.

    Click image for larger version

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    Therefore, once again, my question we reach 144 MHz
    when the maximum pll frequency is 140 MHz.

    Where is my thinking error.

    Best regards

    EbbeSand

  3. #3
    Beginner Beginner EbbeSand is on a distinguished road
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    So I think I found my mistake and now understood at what points in the data sheet are importent for answer my question
    1. pll base frequency
      Without a clock Input fOSC, the PLL gradually slows down to its VCO base frequency and remains there
    2. the VCO frequency range
      min. 260 MHz max 520 MHz --> This correspondence with the pll frequency 288 MHz from the examples
      The assumption with the 144 MHz is therefore wrong one must operate the PLL always larger or equal 260 MHz.
      And that's 288 MHz a good choice.

    One should first understand before asking too fast questions that one can answer to oneself

    Best regards,

    EbbeSand

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