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Thread: AURIX TC27x Lockstep

  1. #1
    New Member New Member bj86 is on a distinguished road
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    AURIX TC27x Lockstep

    Hi,

    I don't understand the lockstep configuration of the AURIX Tricore TC27x.

    It is possible to run CPU 0 and 1 in lockstep mode. So does the Tricore has 3 cores plus 2 checker cores? Or do I have to configure one of the cores as master and one of the cores as checker core (so that two cores are doing the same calculations and one core is left to do something else)?

    Thank you and best regards!

  2. #2
    Advanced Advanced cwunder is on a distinguished road
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    The checker core is not independent of the core it is connected too. The checker core can only be enabled or disabled. The TC27x has three cores (two of which can run with a checker core enabled).

  3. #3
    Beginner Beginner Tobiasw is on a distinguished road
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    Could you please explain, which checker core is associated to which "normal" core?
    I only found the register to activate checker core0 or checker core1. But i did not find the information, which core each of the two is supervising.
    So what is the master core for the checker core1?
    What ist the master core for the checker core0?

    Thank you very much!

  4. #4
    Advanced Advanced cwunder is on a distinguished road
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    Perhaps I don't fully understand your question.

    In the TC27x, both CPU0 and CPU1 instances of the TriCore can be lockstepped. In this terminology Core0 is the master and there is an additional checker core. These two cores can that can be lockstepped together (i.e. Core0 is always there and you can optionally enable the checker core). The lockstep monitoring function will compare the outputs from the master and checker cores and report that a failure has occurred to the Safety Management Unit (SMU) for appropriate action.

    Hope this helps.

  5. #5
    Beginner Beginner Tobiasw is on a distinguished road
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    Ah, thank you very much. now i got it. I did not realize, that each coreX with the lockstep feature have their own master Core, and one checker core, which can be optionally enabled.

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