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Thread: AHB bus interface: Priority DCode vs ICode

  1. #1
    New Member New Member praffeck is on a distinguished road
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    AHB bus interface: Priority DCode vs ICode

    The ARM Cortex-M4 Reference Manual states in section 2.3.1 Bus Interfaces:
    ARM strongly recommends that any external arbitration between the ICode and DCode AHB bus
    interfaces ensures that DCode has a higher priority than ICode.
    Unfortunately, I could not find anything in the XMC4500 Reference Manual, which addresses this statement. The closest I could find was the priority table Table 3-1 in section 3.2 Bus Matrix, which states that request from the CPU will be prioritized over request from other masters, but does not differentiate between CPU requests via ICode and DCode interface.

    So my question is: Does the XMC4500 follow the recommendation? If a request form the ICode bus interface and the DCode bus interface arrive at the Prefetch Unit at the same time, will the DCode request be handled first?

    If I simply overlooked something, while reading the manual, please point me to the correct spot.

    Thank you for your answers.
    Phillip

  2. #2

    Infineon Employee
    Infineon Employee
    jferreira will become famous soon enough
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    Hi,

    Yes, the XMC4500 follows the ARM recommendation.

    Regards,
    Jesus
    The views expressed here are my personal opinions, have not been reviewed or authorized by Infineon and do not necessarily represent the views of Infineon.

  3. #3
    New Member New Member praffeck is on a distinguished road
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    Hi,

    thank you for your help! Much appreciated.

    Regards,
    Phillip

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