I call function

SPITransferStream((const uint16_t * const)&tx_frame, (const uint16_t * const)&rx_frame, 8);
all is working

This doesn't work, i got a Busfault Trap
SPITransferStream((const uint16_t * const)&tx_frame, (const uint16_t * const)&rx_frame, 16);

Here is my code:

>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>> >>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>
#define FIFO_MODE

#define SPI_MISO P2_2
#define SPI_MOSI P2_5
#define SPI_SCLK P2_4


static const XMC_SPI_CH_CONFIG_t spi_config = {

.baudrate = 10000000,
.bus_mode = XMC_SPI_CH_BUS_MODE_MASTER,
.selo_inversion = XMC_SPI_CH_SLAVE_SEL_INV_TO_MSLS,
.parity_mode = XMC_USIC_CH_PARITY_MODE_NONE
};

static const XMC_DMA_CH_CONFIG_t dma_ch_recv_config = {

#ifdef FIFO_MODE
.src_addr = (uint32_t)&(XMC_SPI0_CH1->OUTR),
#else
.src_addr = (uint32_t)&(XMC_SPI0_CH1->RBUF),
#endif
.src_transfer_width = XMC_DMA_CH_TRANSFER_WIDTH_16,
.dst_transfer_width = XMC_DMA_CH_TRANSFER_WIDTH_16,
.src_address_count_mode = XMC_DMA_CH_ADDRESS_COUNT_MODE_NO_CHANGE,
.dst_address_count_mode = XMC_DMA_CH_ADDRESS_COUNT_MODE_INCREMENT,
.src_burst_length = XMC_DMA_CH_BURST_LENGTH_1,
.dst_burst_length = XMC_DMA_CH_BURST_LENGTH_1,
.transfer_flow = XMC_DMA_CH_TRANSFER_FLOW_P2M_DMA,
.transfer_type = XMC_DMA_CH_TRANSFER_TYPE_SINGLE_BLOCK,
.src_handshaking = XMC_DMA_CH_SRC_HANDSHAKING_HARDWARE,
.src_peripheral_request = DMA0_PERIPHERAL_REQUEST_USIC0_SR1_2,
.enable_interrupt = true,
.priority = 7
};


static const XMC_DMA_CH_CONFIG_t dma_ch_send_config = {

#ifdef FIFO_MODE
.dst_addr = (uint32_t)&(XMC_SPI0_CH1->IN),
#else
.dst_addr = (uint32_t)&(XMC_SPI0_CH1->TBUF),
#endif
.src_transfer_width = XMC_DMA_CH_TRANSFER_WIDTH_16,
.dst_transfer_width = XMC_DMA_CH_TRANSFER_WIDTH_16,
.src_address_count_mode = XMC_DMA_CH_ADDRESS_COUNT_MODE_INCREMENT,
.dst_address_count_mode = XMC_DMA_CH_ADDRESS_COUNT_MODE_NO_CHANGE,
#ifdef FIFO_MODE
.src_burst_length = XMC_DMA_CH_BURST_LENGTH_8,
.dst_burst_length = XMC_DMA_CH_BURST_LENGTH_8,
#else
.src_burst_length = XMC_DMA_CH_BURST_LENGTH_1,
.dst_burst_length = XMC_DMA_CH_BURST_LENGTH_1,
#endif
.transfer_flow = XMC_DMA_CH_TRANSFER_FLOW_M2P_DMA,
.transfer_type = XMC_DMA_CH_TRANSFER_TYPE_SINGLE_BLOCK,
.dst_handshaking = XMC_DMA_CH_DST_HANDSHAKING_HARDWARE,
.dst_peripheral_request = DMA0_PERIPHERAL_REQUEST_USIC0_SR0_0,
//.enable_interrupt = true,
};


void SPITransferStream(const uint16_t * const src, const uint16_t *const dst, const uint32_t length) {

XMC_DMA_CH_ClearDestinationPeripheralRequest(XMC_D MA0, 1);
XMC_SPI_CH_TriggerServiceRequest(XMC_SPI0_CH1, 0);


XMC_DMA_CH_SetBlockSize(XMC_DMA0, 0, length);
XMC_DMA_CH_SetBlockSize(XMC_DMA0, 1, length);

XMC_DMA_CH_SetDestinationAddress(XMC_DMA0, 0, (uint32_t)dst);
XMC_DMA_CH_SetSourceAddress(XMC_DMA0, 1, (uint32_t)src);

XMC_DMA_CH_Enable(XMC_DMA0, 0);
XMC_DMA_CH_Enable(XMC_DMA0, 1);
}


void GPDMA0_0_IRQHandler(void) {

XMC_DMA_CH_ClearEventStatus(XMC_DMA0, 0, XMC_DMA_CH_EVENT_TRANSFER_COMPLETE);
XMC_DMA_CH_ClearEventStatus(XMC_DMA0, 1, XMC_DMA_CH_EVENT_TRANSFER_COMPLETE);
}


void SPIInit(void) {

XMC_SPI_CH_Init(XMC_SPI0_CH1, &spi_config);

XMC_SPI_CH_SetWordLength(XMC_SPI0_CH1, 16);
//XMC_SPI_CH_SetFrameLength(XMC_SPI0_CH1, 63);

XMC_USIC_CH_EnableDelayCompensation(XMC_SPI0_CH1);

XMC_SPI_CH_SetInputSource(XMC_SPI0_CH1, XMC_SPI_CH_INPUT_DIN0, USIC0_C1_DX0_P2_2);
XMC_SPI_CH_SetBitOrderMsbFirst(XMC_SPI0_CH1);
XMC_SPI_CH_Start(XMC_SPI0_CH1);

/*GPIO configuration*/
XMC_GPIO_SetMode(SPI_MOSI, XMC_GPIO_MODE_OUTPUT_PUSH_PULL_ALT2);
XMC_GPIO_SetMode(SPI_SCLK, XMC_GPIO_MODE_OUTPUT_PUSH_PULL_ALT2);
XMC_GPIO_SetMode(SPI_MISO, XMC_GPIO_MODE_INPUT_TRISTATE);

XMC_DMA_Init(XMC_DMA0);
XMC_DMA_CH_Init(XMC_DMA0, 0, &dma_ch_recv_config);
XMC_DMA_CH_Init(XMC_DMA0, 1, &dma_ch_send_config);
XMC_DMA_CH_EnableEvent(XMC_DMA0, 0, XMC_DMA_CH_EVENT_TRANSFER_COMPLETE);

#ifdef FIFO_MODE
XMC_USIC_CH_TXFIFO_EnableEvent(XMC_SPI0_CH1, XMC_USIC_CH_TXFIFO_EVENT_CONF_STANDARD);
XMC_USIC_CH_TXFIFO_SetInterruptNodePointer(XMC_SPI 0_CH1, XMC_USIC_CH_TXFIFO_INTERRUPT_NODE_POINTER_STANDARD , 0);
XMC_USIC_CH_TXFIFO_Configure(XMC_SPI0_CH1, 32, XMC_USIC_CH_FIFO_SIZE_16WORDS, 7);
#else
XMC_SPI_CH_SelectInterruptNodePointer(XMC_SPI0_CH1 , XMC_SPI_CH_INTERRUPT_NODE_POINTER_TRANSMIT_SHIFT , 0);
XMC_SPI_CH_EnableEvent(XMC_SPI0_CH1, XMC_SPI_CH_EVENT_TRANSMIT_SHIFT);
#endif

XMC_SPI_CH_SelectInterruptNodePointer(XMC_SPI0_CH1 , XMC_SPI_CH_INTERRUPT_NODE_POINTER_ALTERNATE_RECEIV E, 1);
XMC_SPI_CH_SelectInterruptNodePointer(XMC_SPI0_CH1 , XMC_SPI_CH_INTERRUPT_NODE_POINTER_RECEIVE, 1);
XMC_SPI_CH_EnableEvent(XMC_SPI0_CH1, XMC_SPI_CH_EVENT_STANDARD_RECEIVE | XMC_SPI_CH_EVENT_ALTERNATIVE_RECEIVE);

#ifdef FIFO_MODE
XMC_USIC_CH_RXFIFO_SetInterruptNodePointer(XMC_SPI 0_CH1, XMC_USIC_CH_RXFIFO_INTERRUPT_NODE_POINTER_STANDARD , 1);
XMC_USIC_CH_RXFIFO_EnableEvent(XMC_SPI0_CH1, XMC_USIC_CH_RXFIFO_EVENT_STANDARD);
XMC_USIC_CH_RXFIFO_Configure(XMC_SPI0_CH1, 32, XMC_USIC_CH_FIFO_SIZE_16WORDS, 0);
#endif

NVIC_SetPriority(GPDMA0_0_IRQn, NVIC_EncodePriority(NVIC_GetPriorityGrouping(), 63, 1));
NVIC_EnableIRQ(GPDMA0_0_IRQn);
}