Hello,
I am using the USIC in SPI + WLE Mode to transfer multi-word SPI Frames as master, using both RX and TX FIFOs.
Right now i am facing the problem that I don't really know when the RX data from the last transfer will be available in the RX FIFO.
What I do know, is that it is not immediately after the transfer (TXFIFO = empty). I do not get the full data set then and the RX FIFO fill level is less than what I sent.
.
How many cycles does it take after the physical shifting is complete (i.e. the clock stopped and CS is deactivated) for the value in the DSU to reach the RXFIFO ?
Which event do I have to watch out for? I am thinking MSLS, i am already using it for driving the CS.
Any easy way to do this aside from counting words or polling the fill level ?
