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Thread: XMC4200 USIC/SSC weird FIFO Corruption

  1. #1
    New Member New Member funkyluke is on a distinguished road
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    XMC4200 USIC/SSC weird FIFO Corruption

    Hello Forum,

    I am experiencing a strange behaviour on my XMC4200-based hardware:

    I use USIC0,Ch1 for SPI to communicate with a peripheral chip.
    Since the chip uses variable frame sizes, I chose WLE mode.

    So far that worked out well, i can see the frames on the scope as expected and the responses seemed to be OK on the logic analyzer.

    Here it gets interesting:
    I now want to actually use the responses sent by the external IC in my software, but when I try
    Code:
    XMC_SPI_CH_GetReceivedData(XMC_SPI0_CH1)
    or even
    Code:
    (cvar) = XMC_SPI0_CH1->OUTR
    the SPI TX FIFO seems to become corrupted. I get different frame sizes, different data, extra frames, the lot.
    When I remove all reads of OUTR between the transmissions, everything is fine.

    The reference manual mentions performance considerations when using concurrent access to the FIFO but no real restrictions.
    What is going wrong here?

    Regards,
    Luke

    my Send function:
    Code:
    void spiSendLTFrame(uint8_t cmd, uint16_t addr, uint8_t* data, uint8_t dlen)
    {
      uint8_t i;
    
      XMC_SPI_CH_DisableDataTransmission(XMC_SPI0_CH1);
      XMC_USIC_CH_TXFIFO_PutDataFLEMode(XMC_SPI0_CH1,cmd,SPI_WLE8);
      XMC_USIC_CH_TXFIFO_PutDataFLEMode(XMC_SPI0_CH1,addr,SPI_WLE16);
      for (i = 0; i< dlen; i++)
        {
          if (i == dlen-1)
            XMC_USIC_CH_TXFIFO_PutDataFLEMode(XMC_SPI0_CH1,*data,SPI_WLE8|SPI_EOF);
          else
            XMC_USIC_CH_TXFIFO_PutDataFLEMode(XMC_SPI0_CH1,*data,SPI_WLE8);
    
          data++;
        }
      XMC_SPI_CH_EnableDataTransmission(XMC_SPI0_CH1);
    }
    my FIFO config:
    Code:
    /* Configure receive FIFO settings */
      XMC_USIC_CH_RXFIFO_Configure(XMC_SPI0_CH1,
                                   0U,
                                   (XMC_USIC_CH_FIFO_SIZE_t)XMC_USIC_CH_FIFO_SIZE_8WORDS,
                                   1U);
    
      /* Configure transmit FIFO settings */
      XMC_USIC_CH_TXFIFO_Configure(XMC_SPI0_CH1,
                                   8U,
                                   (XMC_USIC_CH_FIFO_SIZE_t)XMC_USIC_CH_FIFO_SIZE_16WORDS,
                                   1U);
    Last edited by funkyluke; Jul 23rd, 2018 at 07:08 AM.

  2. #2

    Infineon Employee
    Infineon Employee
    jferreira will become famous soon enough
    Join Date
    Oct 2012
    Posts
    626
    Hi,

    Could you trying changing the FIFO configuration to
    Code:
      /* Configure receive FIFO settings */
      XMC_USIC_CH_TXFIFO_Configure(XMC_SPI0_CH1,
                                   0U,
                                   (XMC_USIC_CH_FIFO_SIZE_t)XMC_USIC_CH_FIFO_SIZE_16WORDS,
                                   1U);
    
      /* Configure transmit FIFO settings */
      XMC_USIC_CH_RXFIFO_Configure(XMC_SPI0_CH1,
                                   16U,
                                   (XMC_USIC_CH_FIFO_SIZE_t)XMC_USIC_CH_FIFO_SIZE_8WORDS,
                                   1U);
    From the reference manual
    A FIFO data buffer can only start at a FIFO entry aligned to its size.
    For example, a FIFO buffer containing n entries can only start with FIFO entry 0, n, 2*n,
    3*n, etc. and consists of the FIFO entries [x*n, (x+1)*n-1], with x being an integer number
    (incl. 0). It is not possible to have “holes” with unused FIFO entries within a FIFO buffer,
    whereas there can be unused FIFO entries between two FIFO buffers.
    Regards,
    Jesus
    The views expressed here are my personal opinions, have not been reviewed or authorized by Infineon and do not necessarily represent the views of Infineon.

  3. #3
    New Member New Member funkyluke is on a distinguished road
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    you're correct that was it - thank you!

    I read over that section too quickly, just taking away that the FIFO must be aligned according to possible FIFO sizes, not actual FIFO size.

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