FAQ for miscellaneous Embedded Power IC Topics

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User15216
Level 2
Level 2
The 100 Times-Programmable Page (short: 100TP) can used to store application relevant data, like configuration data, e.g. application variants information, calibration data, etc.
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User15216
Level 2
Level 2
The Vs cap can be used to keep the device supplied to a defined period of time in case of the power loss (VBAT loss) scenario. The addition working time could be used to store application relevant data into the data flash. The size of the Vs cap is calculated by "C = I * t / U". I is the current consumption of the device, e.g. 30mA. t is the time the device should stay active, e.g. 16ms. And U is the voltage delta between the starting voltage of the cap and the reset voltage of the device, e.g. 9V - 3V = 6V. The capacitance will now be: C = 30mA * 16ms / (9V - 3V) = 80µF.
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User15216
Level 2
Level 2
The quiescent current depends on the operation mode of the device. The "sleep mode" provides the lowest quiescent current, which is the range of double digit µA. Please refere to the datasheet for absolute values.
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User15216
Level 2
Level 2
The integrated WDT is inside the microcontroller core, while the WDT1 is located in the system control unit of the device. While the WDT1 is mandatory for automotive applications and cannot be disabled (except for debug mode and stop mode) the WDT is completely controllable by software and freely available to the user application.
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User15216
Level 2
Level 2
The One-Times-Programmable Page (short: OTP) can used to store application relevant data, like configuration data, e.g. application variants information, calibration data, etc.
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User15216
Level 2
Level 2
The max ratings must be obeyed. A diode is recommended in the Vs net before the Vs cap to prevent the Vs cap from being discharged by others than the device itself.
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User15216
Level 2
Level 2
The max ratings must be obeyed. A diode is recommended in the Vs net before the Vs cap to prevent the Vs cap from being discharged by others than the device itself.
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User15216
Level 2
Level 2
The ADC1 is a completely software controlled ADC fully available to the user application. While the ADC2 is a diagnostic ADC which supervises the voltages/temperatures in the device. Programmable thresholds for each channel (voltage) provides a user adjustable generation of interrupts in case a measured voltage is crossing the thresholds.
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User13282
Level 3
Level 3
25 replies posted 10 replies posted 5 replies posted
TLE9844-2QX has 768 Bytes of 100TP. The Firmware supports the write operation with the help of two functions.
• user_nvm_100tp_read
• user_nvm_100tp_write
For further information, please refer to “TLE984x Firmware User Manual” under User Manual in the below link.

https://www.infineon.com/cms/en/product/microcontroller/embedded-power-ics-system-on-chip-/relay-dri...
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User13282
Level 3
Level 3
25 replies posted 10 replies posted 5 replies posted
The TLE9879 is tested according to LV124 test standard.

Is there incorrect LIN communication mode when VS (voltage slope) rise times are slow during TLE9879 power-up sequence test?

In the car, we expect every possible voltage slope and transition. Even slower slopes should not have an influence on the functionality.
When voltage slope transitions are slow during power up sequence test, if the transceiver is in LIN Normal Mode (LNM) instead of LIN Receive Only Mode (LROM), VS undervoltage can be triggered, which causes the LIN to go in Receive-only mode.

LNM to LROM transition is also executed when:
• MODE is configured to LIN Receive-Only Mode or
• Feedback signals of Mode and Slope Mode are not ok or
• VS undervoltage flag (VS_UV_STS) is set or
• LIN transceiver OT_STS or OC_STS are set or
• TXD_TMOUT is set

LROM to LNM transition is executed when:
• MODE is configured to LIN Normal Mode and
• Feedback signals of Mode and Slope Mode are ok and
• VS undervoltage flag (VS_UV_STS) is not set and
• LIN transceiver OT_STS and OC_STS are not set and
• no TXD_TMOUT is set

For further information, please refer to the TLE987xQX User Manual (Page 651) under User Manual in the below link.
https://www.infineon.com/cms/en/product/microcontroller/embedded-power-ics-system-on-chip-/3-phase-b...
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User13282
Level 3
Level 3
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Is it safe to deviate ±x% from the specified attenuator value of ADC1 mentioned in TLE9844 datasheet (P_8.1.x)?

This is the value of capacitor ratio. In case of variation it is "trimmed" with the gain setting. So it is recommended to use (for calculation) only the typical value.
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User13282
Level 3
Level 3
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Question1: To enable the internal measurement on ADC2 of TLE9879, is it possible to implement an expected measurement channel sequence scheme using the Sequence Registers?
Answer1: In general the ADC2 should be used as supervision ADC and it is also used for intrinsic protection mechanisms of the device. (E.g. over temperature switch off). You can adjust certain thresholds to adopt it to the application requirements. (e.g. Vs undervoltage)
For flexible user definable measurements, the ADC1 - the user ADC can be used

Question2: Why some channels are prioritized in TLE987x?
Answer2: In TLE987x Channels 0 - 5 can be fully programmed. Several Sequence registers, especially for channels 6-9, are protected to ensure a fast update of measurement results used for internal diagnosis. Hence the channels 6 and 7 are prioritized and are measured more often. The high prioritization is given by an enabled measurement for each sequence. They cannot be switched off. All other channels are not enabled in much less sequences. Thus, for enabled channels (not 6,7) the update rate (periodicity) is lower, but defined by the channels 6 and 7. Hence, overall periodicity is mainly determined by these two channels.

Question3: Why some sequence registers are not writable by SW in TLE987x?
Answer3: The Channel Controller can be configured by the registers listed in Table 166. The registers which cannot be written by the user have the attribute rwp (can be modified only by hardware and firmware, not by software). xyz_int registers are for internal use, but you can read the configured values. The idea of the ADC2 is mostly for internal purpose with a very strict pre-defines structure and update rate. The user can access / read the ADC2-results and also vary certain thresholds, to make use of the intrinsic device protection. But recommendation is clearly not to change the update rates of the protected channels. Therefore they are also marked as volatile const.

Please Note: The ePower user has to differentiate between ADC2 (just use it as it is) and ADC1, where there are many flexible ways for configuration and control.
For motor control ADC1 has to be used.
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User13282
Level 3
Level 3
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Question1: Is the LIN block exactly the same in the TLE9873QX_40 variant as the one qualified in the TLE9879QX variant used to qualify the other parts?
Answer1: The LIN block is exactly the same.

Question2: Were any of the Test Program changes for the Grade 0 parts related at all to LIN? If so what are the details of those changes?
Answer2: The LIN test program has no changes for Grade 0.

Question3: Do we have any comparative wafer test data between the QXA versions and the new QXW, QXH versions to show that the LIN performance is essentially unchanged?
Answer3: Since there are no changes in LIN test program the test performance is identical.
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Fiz
Moderator
Moderator
Moderator
First like received 50 replies posted 25 replies posted
The device can be updated using FAST LIN BSL bootloader, which is already integrated.
To evaluate this function you can order the uIO-Stick from our preferred design house Hitex.

Link to order the uIO-Stick:

https://www.ehitex.de/en/usb-application-sticks/infineon/2529/uio-stick
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User18205
Level 1
Level 1
Which timer input can be used to capture and count just rising edges of a 5MHz input square wave? Just to capture the count value every 8ms. I've read through timers 2 and 21 they don't seem to support just capture and counting a value and allowing a read. Is this possible without using CPU bandwidth other than to read the value every 8ms. During the 8ms event, the counter would be disabled and once the value is captured and routine is complete then counter would be reset to 0x0000 and restarted. I read the data sheet again and see. I think I'm going to check timer 3 as well.


Edit:
Sorry didn't mean to post this in the FAQ. I did figure this out, just set-up Timer2, on pin 2.5, to read the input at 40MHz, then set up your function to sample the value. Requirement for my application is to sample every 8ms, any slower and it possible that the 16-bit counter will overflow.
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Julella_VLL
Employee
Employee
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The IBIS Model for the TLE987x family is online available together with the PSPICE bridge driver simulation model and can be found here:
https://www.infineon.com/cms/en/product/microcontroller/embedded-power-ics-system-on-chip-/3-phase-b...
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Julella_VLL
Employee
Employee
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TLE985x pins have added robustness which allows them, with additional protection,
to act as off-board pins.
Please not that additional protection via external components (e.g. R-C) is required.
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Julella_VLL
Employee
Employee
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In the GLOBSTR Register you can find the field ANON_ST (TLE987x User Manual section 24.3.2) These bits will change the mode of ADC1:



  • OFF: ADC1 is switched off (Pro: less current consumption, Con: longer wake up time)
  • F_STANDBY: ADC1 is in stand-by mode with fast wake up: (Con: higher current consumption compared with OFF; Pro: faster wake up time compared with OFF)
  • S_STANDBY: see F_STANDBY only with slower wake-up and less current consumption
  • NORMAL: ADC1 is activated
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Julella_VLL
Employee
Employee
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If you want to block all external access to the device by firmware you should not use a BootROM API. If you use a BootROM API the protection is only temporarely and we go away on the next reboot.

For permanent protection you should use FastLIN BSL. Please refer to 4.1 in the BootROM UM.
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Julella_VLL
Employee
Employee
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The Port Output control Registers P0_POCON1 is set by default to value 4.
The user should set the driver strength to "Strong".
Then the phase errors should disappear.
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Julella_VLL
Employee
Employee
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The device can be updated using FAST LIN BSL bootloader, which is already integrated.
To evaluate this function you can order the uIO-Stick from our preferred design house Hitex.

Link to order the uIO-Stick:
https://www.ehitex.de/en/usb-application-sticks/infineon/2529/uio-stick
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Julella_VLL
Employee
Employee
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The TLE984x family has FAST-LIN Protocol support for faster EOL programming.
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Julella_VLL
Employee
Employee
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CS_CUST_BSLSIZE is preconfigured to 4K and cannot be changed.
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Julella_VLL
Employee
Employee
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The debug interface found on the ePower evaluation boards and kits use one of the ARM "standard" debug connector options - the 0.050"/1.27mm 10pin interface.

A typical supplier and part number for the board mounted SMD connector is Samtec FTSH-105-01-L-DV. This is the "unshrouded" version, which reduces board area but makes alignment of the debugger plug more difficult. Shrouded versions are available by adding -ES or -K options to the part number. Free samples are available from Samtec. The main web page for the FTSH family is -> https://www.samtec.com/products/ftsh .

Recommended electrical connections to the ePower device are documented in the "FAQ Application Note for TLE986xQX, TLE987xQX" application note.
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Julella_VLL
Employee
Employee
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Yes, the XMC Link debugger can be used with TLE984x/TLE985x/TLE986x/TLE987x target devices. The XMC4200 microcontroller used in the XMC Link uses the same Segger FW technology as the onboard debugger used in the ePower evalkit designs. The XMC Link hardware uses isolation ICs to buffer the debug output connector. The reference voltage for the debug logic is provided by the target device, and therefore can be used with 3.3V XMC devices and the 5V ePower target devices.
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Julella_VLL
Employee
Employee
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"GainCHx" is the attenuation factor placed before the MUX block, which selects the input signal for the AD converter.

In the electrical characteristics, the "GainCHx" are equivalent to the "ATTx" parameters. The "ATTx" values are specified in the chapter 29.8.1 of the datasheet.

The name mismatch between "GainCHx" and "ATTx" (visible in the formula 22.3) is misleading in the UM (to be corrected in future UM updates).

The "+1" in the formula 22.3 enables to have 255 (with 8-bit ADC) or 1023 (10-bit) at the ADC output, when the voltage to measure reaches its max value. For example: when VS=22V, the ADC output is 255. On the other hand, with 0V at the input, the ADC output is 1. This is equivalent to an error with at 0V at the input, equivalent to 0.4% error with 8-bit, or 0.1% with 10-bit. The calibration unit of the Measurement Core module is dedicated to cancel offset and gain errors out of the signal chain.
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Julella_VLL
Employee
Employee
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NAD and NAC value is set via BootRom function and are not located in the Flash address space.
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Julella_VLL
Employee
Employee
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The Chargepump voltage VCP is stable for VSD >= 8V

The voltage depends on the chargepump load. P_12.1.3 specifies the total voltage range.

The characterisation of the chargepump shows a median voltage of 12.4V for 100nC Gatecharge.
100nC for 6 MOSFETs @20kHz results in 12mA load at VCP.
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Julella_VLL
Employee
Employee
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In order to calculate the power dissipation inside of the Embedded power devices, we recommend to use the power dissipation calculator tool on the Infineon Toolbox.

The toolbox can be downloaded at: https://www.infineon.com/cms/en/tools/landing/infineontoolbox.html
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Julella_VLL
Employee
Employee
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The sheets attached can be used to calculate the timings for ADC 1 and ADC 2.




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Julella_VLL
Employee
Employee
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This parameter specifies an extended voltage operation range for VS below 5.5 V but above 3.0 V. The purpose is to ensure a min. functionality of the device.

In general, the modules do not operate in the specified range anymore. However, functionality is described below:
Affected modules in the device are:
Bridge driver
LDO for VDDP
GPIOs
LDO for VDDEXT

Not affected are:
Microcontroller
Flash

Effects on bridge driver:
The charge-pump can not operate with voltages below 5.4 V (P_1.2.18)
The bridge driver is disabled

Effects on LDO for VDDP:
For Voltages below 5.5 V the LDO cannot provide the desired 5.0 V
There is an output drop at the LDO between 50 and 400 mV (P_2.1.4.), i.e. the voltage regulator operates in low-drop operation
During extended operation VDDP can be defined as: VDDP = VS-50mV(typ)

Effects on the GPIOs:
The GPIOs are affected in their OUTPUT levels and in their INPUT high/low thresholds
Their OUPUT levels are affected accordingly to P_5.1.6 to P_5.1.9

Their INPUT thresholds are affected accordingly to P_5.1.3, P_5.1.17, P_5.1.4, P_5.1.18

Effects on LDO for VDDEXT:
For Voltages below 5.5 V the LDO cannot provide the desired 5.0 V
There is an output drop at the LDO which is defined as in P_2.3.4 and P_2.3.14
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Julella_VLL
Employee
Employee
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The MON pin can be used for battery sensing as one of a possible use case.
In this case, the MON is not protected by the ECUs reverse polarity protection circuit, which could violate the absolute maximum ratings of this pin.
A series resistor RMON of at least 1 kOhm shall be used to limit the current in case of reverse polarity.
The RC time constant has an influence on the Drain-Source Monitoring and the capacitor CMON can be selected according to the required timing.
However, a min. of 10nF is recommended in order to protect the device in case of trasients (ISO pulses, etc.)

4216.attach
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Julella_VLL
Employee
Employee
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What is the value range of AMCLK1_UP_TH in AMCLK_TH_HYS register?
The upper threshold of the analog module clock can be configured between:
0x00~0x3F = 0~63d

If the value range of AMCLK1_UP_TH is 0~63d, is the max value of MI_CLK_UP_TH 35.4375MHz? (MI_CLK_UP_TH = (AMCLK1_UP_TH * LP_CLK) / 32, assumed LP_CLK=18KHz, AMCLK1_UP_TH=63d)
The used formula and the resulting max. value is correct.

What is the value range of AMCLK1_LOW_TH in AMCLK_TH_HYS register?
The lower threshold of the analog module clock can be configured between:
0x00~0x3F = 0~63d

If the value range of AMCLK1_LOW_TH is 0~63d, is the min value of MI_CLK_UP_TH 0MHz? (MI_CLK_LOW_TH = (AMCLK1_LOW_TH * LP_CLK) / 32, assumed LP_CLK=18KHz, AMCLK1_LOW_TH=0)
The used formula and the resulting min. value is correct.

Does the watch-dog have lower limit and upper limit, of 0 MHz rand 35.4735?
The thresholds of the MI_CLK clock watchdog are compared with the independent LP_CLK.
User adjustable thresholds are provided to set the oscillator watchdog to match the user configured MI_CLK.
The MI_CLK is digitally derived from fSYS and should be ≤ 24MHz.
LP_CLK deviates by ±20% → thresholds deviate by 20% aswell
fSYS deviates by ±1.5% → MI_CLK deviates by 1.5% aswell

4217.attach


Is this equal to the MI_CLK value range?

No, see answer question 3
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Julella_VLL
Employee
Employee
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Should GND and LIN_GND be separated because of the EMC?
GND and LIN_GND have to be connected on ECU level to have the same reference.
For EMC optimization reasons LIN_GND can be decoupled with a short trace on the PCB from GND.

What is the max. voltage difference between these grounds?
Maximum difference is ~0.8V (diode forward voltage), depending on temperature etc. As mentioned in question 1, all GND pins must be connected on PCB level to a common GND.
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Julella_VLL
Employee
Employee
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It is possible.
Only difference is, you still have to set all 6 channels to PWM mode.
Additional recommendations:
Leave Bridge driver pins HS3 ,SH3 and LS3 open
Turn off CCU6 modulation for CC62 and COUT62
For optimization reasons, we do recommend the TLE986x family of our Embedded Power ICs.
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Julella_VLL
Employee
Employee
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This example code helps to download firmware via uIO Stick using VS, LIN and GND.

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Julella_VLL
Employee
Employee
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Note: this is Valid for the BF-Step.
Information about the NVM-Protection can be found in the BootROM UM Rev. 1.4 Chapter 4.4.2.7 and Chapter 5.4.5
The UART BLS Mode has 6 Modes and entering them is determined by the Header-Block of the Data Sent. Mode Number 6 Handles the NVM Protection via a Password. Once a Password is set, the use of some other Modes is restricted as can be read in Ch.:
4.4.2.2 (Programming to RAM is not allowed if PW is set)
4.4.2.4 (Code/Dta download to NVM not accessable if PW is set)
4.4.3.6 (NVM Erase is not accessible if PW is set)
In Mode 6 (Ch. 4.4.2.6) the user has the possibility to set a Password.
If the Device is not protected, the sent password will enable the protection.
If the Device is protected, and the passwords match, depending on the MSB of the Password either the Code Region or the Code and Data Region are deleted.
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Julella_VLL
Employee
Employee
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Infineon is using state-of-the-art automotive package components.
Overmolding causes different / new stresses at product level compared to traditional board assembly and vary depending on the process. It is in the customer responsibility - similar as bare die handling.
Therefore, Infineon cannot give any recommendation on the overmolding process or deliver any reliability statement regarding the Modules, neither regarding lifetime assessment nor probability of failures.
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Julella_VLL
Employee
Employee
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The capacitor values ensure the stability of the power supplies under load jump conditions. Load jumps in general are sudden changes of the load of the respective regulator output (vs. line jumps, which are sudden changes at the input of a regulator).
The load jumps definitions for the capacitors selection are specified by design and are:
CVDDP2: 2mA to IVDDP with a slew rate dI/dt=100mA/µs
CVDDC2: 2mA to 40mA with a slew rate dI/dt=100mA/µs
CVDDEXT2: 2mA to IVDDEXT with a slew rate dI/dt=10mA/µs
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Julella_VLL
Employee
Employee
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This depends on the operating power mode of the device. The behavior is as following:

Active mode: the BDRV is in active mode, VSD is powered. In this case, the MOSFET is driven by the active drive current, the RGGND will not be active

Sleep mode: VSD and VS are powered but the device is in sleep mode. In this case the BDRV is power down and RGGND is enabled, and the MOSFET will be pull down (breaking)

VSD and VS are not powered: RGGND will not work, and the MOSFET is floating if there is no external pull down resistor
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