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Thread: FAQ for miscellaneous Embedded Power IC Topics

  1. #31
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    What is the reduced functionality for VS_AMmin in the datasheet (P_1.2.3)?

    This parameter specifies an extended voltage operation range for VS below 5.5 V but above 3.0 V. The purpose is to ensure a min. functionality of the device.

    In general, the modules do not operate in the specified range anymore. However, functionality is described below:
    Affected modules in the device are:
    Bridge driver
    LDO for VDDP
    GPIOs
    LDO for VDDEXT

    Not affected are:
    Microcontroller
    Flash

    Effects on bridge driver:
    The charge-pump can not operate with voltages below 5.4 V (P_1.2.18)
    The bridge driver is disabled

    Effects on LDO for VDDP:
    For Voltages below 5.5 V the LDO cannot provide the desired 5.0 V
    There is an output drop at the LDO between 50 and 400 mV (P_2.1.4.), i.e. the voltage regulator operates in low-drop operation
    During extended operation VDDP can be defined as: VDDP = VS-50mV(typ)

    Effects on the GPIOs:
    The GPIOs are affected in their OUTPUT levels and in their INPUT high/low thresholds
    Their OUPUT levels are affected accordingly to P_5.1.6 to P_5.1.9

    Their INPUT thresholds are affected accordingly to P_5.1.3, P_5.1.17, P_5.1.4, P_5.1.18

    Effects on LDO for VDDEXT:
    For Voltages below 5.5 V the LDO cannot provide the desired 5.0 V
    There is an output drop at the LDO which is defined as in P_2.3.4 and P_2.3.14
    The views expressed here are my personal opinions, have not been reviewed or authorized by Infineon and do not necessarily represent the views of Infineon.

  2. #32
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    MON Input Filter recommendations

    The MON pin can be used for battery sensing as one of a possible use case.
    In this case, the MON is not protected by the ECUs reverse polarity protection circuit, which could violate the absolute maximum ratings of this pin.
    A series resistor RMON of at least 1 kOhm shall be used to limit the current in case of reverse polarity.
    The RC time constant has an influence on the Drain-Source Monitoring and the capacitor CMON can be selected according to the required timing.
    However, a min. of 10nF is recommended in order to protect the device in case of trasients (ISO pulses, etc.)

    Click image for larger version

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    The views expressed here are my personal opinions, have not been reviewed or authorized by Infineon and do not necessarily represent the views of Infineon.

  3. #33
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    Value range of AMCLK1_UP_TH and AMCLK1_LOW_TH

    What is the value range of AMCLK1_UP_TH in AMCLK_TH_HYS register?
    The upper threshold of the analog module clock can be configured between:
    0x00~0x3F = 0~63d

    If the value range of AMCLK1_UP_TH is 0~63d, is the max value of MI_CLK_UP_TH 35.4375MHz? (MI_CLK_UP_TH = (AMCLK1_UP_TH * LP_CLK) / 32, assumed LP_CLK=18KHz, AMCLK1_UP_TH=63d)
    The used formula and the resulting max. value is correct.

    What is the value range of AMCLK1_LOW_TH in AMCLK_TH_HYS register?
    The lower threshold of the analog module clock can be configured between:
    0x00~0x3F = 0~63d

    If the value range of AMCLK1_LOW_TH is 0~63d, is the min value of MI_CLK_UP_TH 0MHz? (MI_CLK_LOW_TH = (AMCLK1_LOW_TH * LP_CLK) / 32, assumed LP_CLK=18KHz, AMCLK1_LOW_TH=0)
    The used formula and the resulting min. value is correct.

    Does the watch-dog have lower limit and upper limit, of 0 MHz rand 35.4735?
    The thresholds of the MI_CLK clock watchdog are compared with the independent LP_CLK.
    User adjustable thresholds are provided to set the oscillator watchdog to match the user configured MI_CLK.
    The MI_CLK is digitally derived from fSYS and should be ≤ 24MHz.
    LP_CLK deviates by ±20% → thresholds deviate by 20% aswell
    fSYS deviates by ±1.5% → MI_CLK deviates by 1.5% aswell

    Click image for larger version

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    Is this equal to the MI_CLK value range?

    No, see answer question 3
    The views expressed here are my personal opinions, have not been reviewed or authorized by Infineon and do not necessarily represent the views of Infineon.

  4. #34
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    Voltage difference between LIN_GND and GND

    Should GND and LIN_GND be separated because of the EMC?
    GND and LIN_GND have to be connected on ECU level to have the same reference.
    For EMC optimization reasons LIN_GND can be decoupled with a short trace on the PCB from GND.

    What is the max. voltage difference between these grounds?
    Maximum difference is ~0.8V (diode forward voltage), depending on temperature etc. As mentioned in question 1, all GND pins must be connected on PCB level to a common GND.
    The views expressed here are my personal opinions, have not been reviewed or authorized by Infineon and do not necessarily represent the views of Infineon.

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    Can the TLE987x family drive 4 MOSFETs (H-Bridge) instead of 6 MOSFETs?

    It is possible.
    Only difference is, you still have to set all 6 channels to PWM mode.
    Additional recommendations:
    Leave Bridge driver pins HS3 ,SH3 and LS3 open
    Turn off CCU6 modulation for CC62 and COUT62
    For optimization reasons, we do recommend the TLE986x family of our Embedded Power ICs.
    The views expressed here are my personal opinions, have not been reviewed or authorized by Infineon and do not necessarily represent the views of Infineon.

  6. #36
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    How to update NAC and NAD via uIO Stick?

    This example code helps to download firmware via uIO Stick using VS, LIN and GND.

    TLE987x_02_NAC_NAD_Change_RUNNING_LIGHTS_EXAMPLE_TLE987X.zip
    The views expressed here are my personal opinions, have not been reviewed or authorized by Infineon and do not necessarily represent the views of Infineon.

  7. #37
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    How can I protect my Program and Data from Read out?

    Note: this is Valid for the BF-Step.
    Information about the NVM-Protection can be found in the BootROM UM Rev. 1.4 Chapter 4.4.2.7 and Chapter 5.4.5
    The UART BLS Mode has 6 Modes and entering them is determined by the Header-Block of the Data Sent. Mode Number 6 Handles the NVM Protection via a Password. Once a Password is set, the use of some other Modes is restricted as can be read in Ch.:
    4.4.2.2 (Programming to RAM is not allowed if PW is set)
    4.4.2.4 (Code/Dta download to NVM not accessable if PW is set)
    4.4.3.6 (NVM Erase is not accessible if PW is set)
    In Mode 6 (Ch. 4.4.2.6) the user has the possibility to set a Password.
    If the Device is not protected, the sent password will enable the protection.
    If the Device is protected, and the passwords match, depending on the MSB of the Password either the Code Region or the Code and Data Region are deleted.
    The views expressed here are my personal opinions, have not been reviewed or authorized by Infineon and do not necessarily represent the views of Infineon.

  8. #38
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    Do you have any recommendation on overmolding TLE98xx products?

    Infineon is using state-of-the-art automotive package components.
    Overmolding causes different / new stresses at product level compared to traditional board assembly and vary depending on the process. It is in the customer responsibility - similar as bare die handling.
    Therefore, Infineon cannot give any recommendation on the overmolding process or deliver any reliability statement regarding the Modules, neither regarding lifetime assessment nor probability of failures.
    The views expressed here are my personal opinions, have not been reviewed or authorized by Infineon and do not necessarily represent the views of Infineon.

  9. #39
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    Where does the specification for the buffer capacitors come from?

    The capacitor values ensure the stability of the power supplies under load jump conditions. Load jumps in general are sudden changes of the load of the respective regulator output (vs. line jumps, which are sudden changes at the input of a regulator).
    The load jumps definitions for the capacitors selection are specified by design and are:
    CVDDP2: 2mA to IVDDP with a slew rate dI/dt=100mA/µs
    CVDDC2: 2mA to 40mA with a slew rate dI/dt=100mA/µs
    CVDDEXT2: 2mA to IVDDEXT with a slew rate dI/dt=10mA/µs
    The views expressed here are my personal opinions, have not been reviewed or authorized by Infineon and do not necessarily represent the views of Infineon.

  10. #40
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    Are the internal gate resistances (RGGND) always connected to GND?

    This depends on the operating power mode of the device. The behavior is as following:

    Active mode: the BDRV is in active mode, VSD is powered. In this case, the MOSFET is driven by the active drive current, the RGGND will not be active

    Sleep mode: VSD and VS are powered but the device is in sleep mode. In this case the BDRV is power down and RGGND is enabled, and the MOSFET will be pull down (breaking)

    VSD and VS are not powered: RGGND will not work, and the MOSFET is floating if there is no external pull down resistor
    The views expressed here are my personal opinions, have not been reviewed or authorized by Infineon and do not necessarily represent the views of Infineon.

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