Mar 15, 2018
08:54 AM
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Mar 15, 2018
08:54 AM
Hello I try to start the 16 Bit EBU on my new XMC4700 board
On an 4500 other port pin mapping same configuartion It works
On an 4700 It doesn't work
or
If any one will have a solution to run XMC7000 EBU Interface.
Thanks
EbbeSand
// EBU - address pins
#define EBU_AD0 P0_2
#define EBU_AD1 P0_3
#define EBU_AD2 P0_4
#define EBU_AD3 P0_5
#define EBU_AD4 P3_5
#define EBU_AD5 P3_6
#define EBU_AD6 P0_7
#define EBU_AD7 P0_8
#define EBU_AD8 P4_0
#define EBU_AD9 P4_1
#define EBU_AD10 P1_6
#define EBU_AD11 P1_7
#define EBU_AD12 P1_8
#define EBU_AD13 P1_9
#define EBU_AD14 P1_2
#define EBU_AD15 P1_3
// EBU - control pins common used signals
#define EBU_CS0 P3_2
#define EBU_WR P3_1
#define EBU_RD P3_0
#define EBU_A19 P6_4 // (On XMC4500 I use a Port Pin to Handel Command / Data)
/* EBU Configuration */
XMC_EBU_t *const ebumodule = (XMC_EBU_t *)EBU;
//Clock Control Register; CLC
XMC_EBU_CONFIG_t ebuobj = {
.ebu_clk_config.ebu_clock_divide_ratio = XMC_EBU_CLOCK_DIVIDED_BY_2,
.ebu_clk_config.ebu_div2_clk_mode = XMC_EBU_DIV2_CLK_MODE_ON ,
.ebu_clk_config.ebu_clk_mode = XMC_EBU_CLK_MODE_SYNCHRONOUS_TO_CPU ,
.ebu_mode_config.ebu_extlock = false,
.ebu_mode_config.ebu_arbsync = true,
.ebu_mode_config.ebu_arbitration_mode = XMC_EBU_ARB_MODE_SOLE_MASTER_MODE,
.ebu_mode_config.bus_timeout_control = 0xFFU,
.ebu_mode_config.ebu_ale_mode = XMC_EBU_ALE_OUTPUT_IS_INV_ADV,
.ebu_free_pins_to_gpio.address_pins_gpio = 0x1FFU,
.ebu_free_pins_to_gpio.adv_pin_gpio = false
};
//
// Region Display BUSRCON0, BUSWCON0
XMC_EBU_REGION_t ebureadwriteconfig = {
.read_config.ebu_region_no = 0x0U,
.read_config.ebu_bus_read_config.ebu_burst_length_sync = 0x3U,
.read_config.ebu_bus_read_config.ebu_burst_buffer_sync_mode = 0x0U,
.read_config.ebu_bus_read_config.ebu_read_stages_synch = 0x0U,
.read_config.ebu_bus_read_config.ebu_burst_flash_clock_feedback = XMC_EBU_BURST_FLASH_CLOCK_FEEDBACK_DISABLE,
.read_config.ebu_bus_read_config.ebu_burst_flash_clock_mode = 0x0U,
.read_config.ebu_bus_read_config.ebu_byte_control = XMC_EBU_BYTE_CONTROL_FOLLOWS_WRITE_ENABLE_SIGNAL_TIMMING,
.read_config.ebu_bus_read_config.ebu_device_addressing_mode = XMC_EBU_DEVICE_ADDRESSING_MODE_16_BITS,
.read_config.ebu_bus_read_config.ebu_device_type = XMC_EBU_DEVICE_TYPE_MUXED_ASYNCHRONOUS_TYPE,
.read_config.ebu_bus_read_config.address_cycles = 0x2U, // Taktzyklen, die Adresse mit /ALE anliegt (EBU_CLK, nicht SDOCLKO); >= 1
.read_config.ebu_bus_read_config.ebu_programmed_wait_states_for_read_accesses = 0x0U, // Taktzyklen -1 , die Daten empfangen wird (Sample am Ende) (EBU_CLK, nicht BFCLKO); >= 1
.read_config.ebu_bus_read_config.address_hold_cycles = 0x0U,
.read_config.ebu_bus_read_config.command_delay_lines = 0x3U,
.read_config.ebu_bus_read_config.ebu_ext_data = 0x0U,
.read_config.ebu_bus_read_config.ebu_freq_ext_clk_pin = 0x1U, // Bei durchgehenden Takt ignoriert => siehe Region0
.read_config.ebu_bus_read_config.ebu_recovery_cycles_between_different_regions = 0x2U,
.read_config.ebu_bus_read_config.ebu_recovery_cycles_after_read_accesses = 0x0U,
.read_config.ebu_bus_read_config.ebu_burst_buffer_sync_mode = 1, // Kontinuierlicher Burst Modus, ebu_burst_length_sync wird ignoriert
.read_config.ebu_bus_read_config.ebu_burst_flash_clock_mode = 0, // BFCLKO immer an
.read_config.ebu_bus_read_config.ebu_burst_flash_clock_feedback = 0, // BFCLKI nicht genutzt
.read_config.ebu_bus_read_config.ebu_burst_buffer_sync_mode = 1, // Einfache Synchronisation, minimale Latenz
.write_config.ebu_region_no = 0x0U,
.write_config.ebu_bus_write_config.ebu_burst_length_sync = 0x03U,
.write_config.ebu_bus_write_config.ebu_burst_buffer_sync_mode = 0x0U,
.write_config.ebu_bus_write_config.ebu_byte_control = XMC_EBU_BYTE_CONTROL_FOLLOWS_WRITE_ENABLE_SIGNAL_TIMMING,
.write_config.ebu_bus_write_config.ebu_device_type = XMC_EBU_DEVICE_TYPE_MUXED_ASYNCHRONOUS_TYPE,
.write_config.ebu_bus_write_config.ebu_device_addressing_mode = XMC_EBU_DEVICE_ADDRESSING_MODE_16_BITS,
.write_config.ebu_bus_write_config.address_cycles = 0x0U, // Taktzyklen, die Adresse mit /ALE anliegt (EBU_CLK, nicht SDOCLKO); >= 1
.write_config.ebu_bus_write_config.ebu_programmed_wait_states_for_write_accesses = 0x0U, // Taktzyklen-1, die Daten ausgegeben wird (mit /WE) (EBU_CLK, nicht SDOCLKO); >= 1
.write_config.ebu_bus_write_config.address_hold_cycles = 0x0U,
.write_config.ebu_bus_write_config.command_delay_lines = 0x3U,
.write_config.ebu_bus_write_config.ebu_ext_data = 0x0U,
.write_config.ebu_bus_write_config.ebu_freq_ext_clk_pin = 0x1U, // Bei durchgehenden Takt ignoriert => siehe Region0
.write_config.ebu_bus_write_config.ebu_recovery_cycles_between_different_regions = 0x2U,
.write_config.ebu_bus_write_config.ebu_recovery_cycles_after_write_accesses = 0x3U,
.write_config.ebu_bus_write_config.ebu_burst_buffer_sync_mode = 1, // Kontinuierlicher Burst Modus, ebu_burst_length_sync wird ignoriert
};
// Configuration for all Pins
XMC_GPIO_CONFIG_t config;
config.mode = XMC_GPIO_MODE_OUTPUT_PUSH_PULL;
config.output_level = XMC_GPIO_OUTPUT_LEVEL_HIGH;
config.output_strength = XMC_GPIO_OUTPUT_STRENGTH_STRONG_SHARP_EDGE;
XMC_GPIO_Init(EBU_AD0, &config); XMC_GPIO_SetHardwareControl(EBU_AD0, XMC_GPIO_HWCTRL_PERIPHERAL2); // Bus line AD0..AD15
XMC_GPIO_Init(EBU_AD1, &config); XMC_GPIO_SetHardwareControl(EBU_AD1, XMC_GPIO_HWCTRL_PERIPHERAL2);
XMC_GPIO_Init(EBU_AD2, &config); XMC_GPIO_SetHardwareControl(EBU_AD2, XMC_GPIO_HWCTRL_PERIPHERAL2);
XMC_GPIO_Init(EBU_AD3, &config); XMC_GPIO_SetHardwareControl(EBU_AD3, XMC_GPIO_HWCTRL_PERIPHERAL2);
XMC_GPIO_Init(EBU_AD4, &config); XMC_GPIO_SetHardwareControl(EBU_AD4, XMC_GPIO_HWCTRL_PERIPHERAL2);
XMC_GPIO_Init(EBU_AD5, &config); XMC_GPIO_SetHardwareControl(EBU_AD5, XMC_GPIO_HWCTRL_PERIPHERAL2);
XMC_GPIO_Init(EBU_AD6, &config); XMC_GPIO_SetHardwareControl(EBU_AD6, XMC_GPIO_HWCTRL_PERIPHERAL2);
XMC_GPIO_Init(EBU_AD7, &config); XMC_GPIO_SetHardwareControl(EBU_AD7, XMC_GPIO_HWCTRL_PERIPHERAL2);
XMC_GPIO_Init(EBU_AD8, &config); XMC_GPIO_SetHardwareControl(EBU_AD8, XMC_GPIO_HWCTRL_PERIPHERAL2);
XMC_GPIO_Init(EBU_AD9, &config); XMC_GPIO_SetHardwareControl(EBU_AD9, XMC_GPIO_HWCTRL_PERIPHERAL2);
XMC_GPIO_Init(EBU_AD10, &config); XMC_GPIO_SetHardwareControl(EBU_AD10, XMC_GPIO_HWCTRL_PERIPHERAL2);
XMC_GPIO_Init(EBU_AD11, &config); XMC_GPIO_SetHardwareControl(EBU_AD11, XMC_GPIO_HWCTRL_PERIPHERAL2);
XMC_GPIO_Init(EBU_AD12, &config); XMC_GPIO_SetHardwareControl(EBU_AD12, XMC_GPIO_HWCTRL_PERIPHERAL2);
XMC_GPIO_Init(EBU_AD13, &config); XMC_GPIO_SetHardwareControl(EBU_AD13, XMC_GPIO_HWCTRL_PERIPHERAL2);
XMC_GPIO_Init(EBU_AD14, &config); XMC_GPIO_SetHardwareControl(EBU_AD14, XMC_GPIO_HWCTRL_PERIPHERAL2);
XMC_GPIO_Init(EBU_AD15, &config); XMC_GPIO_SetHardwareControl(EBU_AD15, XMC_GPIO_HWCTRL_PERIPHERAL2);
XMC_GPIO_Init(EBU_CS0, &config); XMC_GPIO_SetHardwareControl(EBU_CS0, XMC_GPIO_HWCTRL_PERIPHERAL2); //Chip Select
XMC_GPIO_Init(EBU_RD, &config); XMC_GPIO_SetHardwareControl(EBU_RD, XMC_GPIO_HWCTRL_PERIPHERAL2); // Read Requested
XMC_GPIO_Init(EBU_WR, &config); XMC_GPIO_SetHardwareControl(EBU_WR, XMC_GPIO_HWCTRL_PERIPHERAL2); // Write Requested
XMC_GPIO_Init(EBU_A19, &config); XMC_GPIO_SetHardwareControl(EBU_A19, XMC_GPIO_HWCTRL_PERIPHERAL2); // Command or Data
/*Base Address of external GRAM Data memory region */
#define EBU_EXT_RAM_REGION_BASE 0x60000000UL //RS = 0
/*Base Address of external device memory region */
#define EBU_EXT_DEVICE_REGION_BASE 0xA0000000UL
/*Base Address of external Command */
#define EBU_EXT_COMMAND_REGION_BASE 0x60080000UL //RS = 1
On an 4500 other port pin mapping same configuartion It works
C/D PIN HIGH
*(volatile uint16_t *)(EBU_EXT_RAM_REGION_BASE) = Adresse;
*(volatile uint16_t *)(EBU_EXT_RAM_REGION_BASE) = data;
On an 4700 It doesn't work
C/D PIN HIGH
*(volatile uint16_t *)(EBU_EXT_RAM_REGION_BASE)= Adresse;
*(volatile uint16_t *)(EBU_EXT_RAM_REGION_BASE) = data;
or
*(volatile uint16_t *)(EBU_EXT_COMMAND_REGION_BASE) = Adresse;
*(volatile uint16_t *)(EBU_EXT_RAM_REGION_BASE) = data;
If any one will have a solution to run XMC7000 EBU Interface.
Thanks
EbbeSand
2 Replies
Jul 08, 2018
03:31 PM
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Jul 08, 2018
03:31 PM
Hi Ebbesand,
Did you happen to find solution for EBU interface on XMC4700 ?
I am trying to implement EBU interface with NAND flash and having same issue. Could you please provide me more information how you resolved this issue ?
Thanks
Query1920
Did you happen to find solution for EBU interface on XMC4700 ?
I am trying to implement EBU interface with NAND flash and having same issue. Could you please provide me more information how you resolved this issue ?
Thanks
Query1920
Feb 08, 2019
02:18 AM
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Feb 08, 2019
02:18 AM
Hi Query1920,
sorry for the slow Response on your question, but I did't saw that you send me a question on my post
yes the EBU Interface is running
For the Adressing I use the following definition
and it works
Best regards
Ebbe Sand
sorry for the slow Response on your question, but I did't saw that you send me a question on my post
yes the EBU Interface is running
For the Adressing I use the following definition
//--------------------------------------------------------------
// Adressen vom EBU um auf das Display zuzugreifen
// Regio 0 = CS0 => BaseAdr 0x60000000
// RS-Pin = Generic EBU__Address [23:16]__EBU.A19 => Offset 0x01000000
//--------------------------------------------------------------
/*Base Address Control A19 */
/*Command base address assignment */
/*Base Address of external CTRL region */
#define EBU_EXT_CTRL_REGION_BASE 0x60000000UL
#define CTRL EBU_EXT_CTRL_REGION_BASE
/*Base Address of external RAM memory region */
/*Base Address of external device memory region */
/*GRAM base address assignment */
#define EBU_EXT_DEVICE_REGION_BASE 0xA0100000UL
#define EBU_EXT_RAM_REGION_BASE 0x60100000UL
#define GRAM EBU_EXT_RAM_REGION_BASE
#define LCD_REG ( *((volatile uint16_t *) CTRL))
#define LCD_RAM ( *((volatile uint16_t *) GRAM))
and it works
Best regards
Ebbe Sand