external interrupts with XC888

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Hello,

We use XC888 for educational purposes. Today, one of my students tried to use an extarnal interrupt (external interrupt1).
To our amazement the interrupt was only executed once. The user's manual states the pending bit will be cleared by hardware
when branching to the ISR.

In the UM there is a description of the IRCON0 register (p 5-25) stating that these bits (EXINT0 and EXTINT1) :

This bit is set by hardware and can only be cleared by software.
0 Interrupt event has not occurred.
1 Interrupt event has occurred.
These bits are set by corresponding active edge event i.e. falling/rising/both. These flags are
‘dummy’ and has no effect on the respective interrupt signal to core. Instead, the corresponding
TCON flag is the interrupt request to the core - it is sufficient to poll and clear the TCON flag.

It seems these bits are NOT dummy, and must becleared after entering the ISR.
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All my external interrupts on the XC878 (which is very similar) contain code like this:
IRCON0 &= ~(1 << BIT_EXINT3);

I do this because the ISR is serviced by several interrupt sources and I use the bit to distinguish which of them triggered the ISR.

In the XC878 UM the same statement is only made for external interrupts 0 and 1. The documentation of the corresponding TCON flag states:
"Cleared by hardware when processor vectors to interrupt routine. Can also be cleared by software."

With that in mind the statement "it is sufficient to poll and clear the TCON flag" is false/misleading, because there is no reason to interact with the TCON flag. Thus I doubt the validity of the remaining statement. I can confirm that it works if the bit in IRCON0 is cleared.
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