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Thread: LIN on xmc4800

  1. #1
    Beginner Beginner j_aug is on a distinguished road
    Join Date
    Feb 2018

    LIN on xmc4800

    Hi, I am trying to do some modifications for uart drivers for xmc4800 (on relax kit xmc 4800) and extending them to LIN drivers.
    When I followed the documentation of Infineon reference manual for LIN support, in page 18-72 under
    18.3.5 Hardware LIN Support gave some explaination as follows:

    A complete LIN frame contains the following symbols:
    • Synchronization break:
    The master sends a synchronization break to signal the beginning of a new frame. It
    contains at least 13 consecutive bit times at 0 level, followed by at least one bit time
    at 1 level (corresponding to 1 stop bit). Therefore, TBUF11 if the transmit buffer is
    used, (or IN11 if the FIFO buffer is used) has to be written with 0 (leading to a frame
    with SOF followed by 12 data bits at 0 level).
    A slave device shall detect 11 consecutive bit times at 0 level, which done by the
    synchronization break detection. Bit PSR.SBD is set if such an event is detected and
    a protocol interrupt can be generated. Additionally, the received data value of 0
    appears in the receive buffer and a format error is signaled.

    Following that I have made changes in the following lines of code.

    if ( !(USIC_CH_TCSR_TDV_Msk & tmp_pChannel->TCSR) )
          tmp_pChannel->TBUF[0] = ((arg_ByteToSend << USIC_CH_TBUF_TDATA_Pos) & USIC_CH_TBUF_TDATA_Msk);
    into following lines of code

    int j =0;
            		    	//tmp_pChannel->TBUF[j] &= ~(1 << tmp_pChannel->TBUF[j]);
    if ( !(USIC_CH_TCSR_TDV_Msk & tmp_pChannel->TCSR) )
          tmp_pChannel->TBUF[12] = ((arg_ByteToSend << USIC_CH_TBUF_TDATA_Pos) & USIC_CH_TBUF_TDATA_Msk);

    But I am unable to generate break field for LIN following the documentation. Can anyone help in this.

  2. #2
    Intermediate Intermediate
    Infineon Employee
    Infineon Employee
    DRubeša will become famous soon enough
    Join Date
    Jul 2016

    this TBUF11 you need to undestand quite directly so, the idea is not to fill TBUF from 0 to 11 with 0, but to write TBUF11 with 0 and that should be it. How does this work? Ever TBUF or IN buffer if you use FIFO encodes also the TCI based on the address on a buffer. Search for " Transmit Control Information" chapter for more details, but in short; TBUF0 has TCI of 0b00000, TBUF1 has TCI of 0b00001, and finally TBUF31 has TCI of 0b11111. This TCI information contains some additional configuration settings that can be used dynamically. Which setting are effect by TCI you can find in the mentioned chapter but what is important for you is FLE. That is data frame length. To be able to use this feature, you should enable bit TCSR.FLEMD. This is exactly the first sentence of the "Hardware LIN support" chapter that you also quoted:

    In order to support the LIN protocol, bit TCSR.FLEMD = 1 should be set for the master.
    Now that bit TCSR.FLEMD is enabled, data frame length will be dynamically set and the value which will be set is the value that TCI this case it is 11 so that means "please write to the bus 11 consecutive bit times at 0 level". And as you already noticed this is exactly what the LIN slave expects.

    Best regards,
    Last edited by DRubeša; Feb 13th, 2018 at 06:48 AM.
    The views expressed here are my personal opinions, have not been reviewed or authorized by Infineon and do not necessarily represent the views of Infineon.

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