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Thread: Err (Error output) of ISO1I811T always stays low .

  1. #1
    New Member New Member Abhay Bhanushali is on a distinguished road
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    Err (Error output) of ISO1I811T always stays low .

    Hello,

    This is Abhay.
    I have a problem in reading the inputs using spi on ISO1I811T chip. According to datasheet , Error out (/ERR) stays high for normal operation I get this Signal low all the time and At ROSC pin the regulated
    voltage is zero(should be 1.4v).
    I have checked VBB-GNDBB(24V) and VCC-GND(3.3v) , thats ok.

    Plz Find Attached ckt diagram for reference, and please point out if there's something wrong.

    please reply ASAP

    Thanks.
    ?????? ?????? iso1i811t_ckt.JPG‎  

  2. #2
    New Member New Member Jean-Marc is on a distinguished road
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    Hello,
    i do not know if this will help but it is written in page 14 in the datasheet the following remark:
    Important: Since the UV and MV (as well as the TE and W4S) bits used for generating the ERR signal are preset
    to High during UVLO, the ERR pin is Low after power up. Therefore the ERR signal requires to be explicitly cleared
    after power up. At least one read access to the GLERR and INTERR registers is needed to update those status
    bits and thus release the ERR pin.
    I hope this would help you
    Bests

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