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Jan 23, 2018
06:03 AM
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Jan 23, 2018
06:03 AM
Hi all,
we have Problems using spi slave on a XMC 4700.
Settings:
XMC4700 with Dave 4 APPs, Project is attached.
Clock is generated external an feed to the XMC ( frequeny generator ) SCLK input.
Data Transfer is prepared for DMA.
Interrupt on PIN 0.8 on falling edge is enabled ( same CLK signal as 5.2 ) and then P5.5 ist
driven low, which will drive by bridge P5.1 input ( slave selct ).
The CPU should shift out every time the same, but doesn't depending on the Frequency, e.g. 20 Mhz forks fine.
Plase take a look at the scope timings.
Can you helP ???
Thanks & Regards
TSB
we have Problems using spi slave on a XMC 4700.
Settings:
XMC4700 with Dave 4 APPs, Project is attached.
Clock is generated external an feed to the XMC ( frequeny generator ) SCLK input.
Data Transfer is prepared for DMA.
Interrupt on PIN 0.8 on falling edge is enabled ( same CLK signal as 5.2 ) and then P5.5 ist
driven low, which will drive by bridge P5.1 input ( slave selct ).
The CPU should shift out every time the same, but doesn't depending on the Frequency, e.g. 20 Mhz forks fine.
Plase take a look at the scope timings.
Can you helP ???
Thanks & Regards
TSB
- Tags:
- IFX
4 Replies
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Feb 15, 2018
05:56 AM
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Feb 15, 2018
05:56 AM
Just wanne bring this up.
Is no one from Infineon able to help ?
This seems to be an issue I think.
I just only use thew Dave APP.
Going down to XMC lib doe
Is no one from Infineon able to help ?
This seems to be an issue I think.
I just only use thew Dave APP.
Going down to XMC lib doe
Mar 07, 2018
12:07 PM
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Mar 07, 2018
12:07 PM
Hi,
The problem is that you are using a continuous clock. Normally a master will assert the CS and start clocking the data. When the data transfer is finished, clock is stopped and CS is deasserted.
Please notice that waiting for
When using a proper SPI master, the master will stop the clock and deassert the CS when the total number of bytes are received.
Regards,
Jesus
The problem is that you are using a continuous clock. Normally a master will assert the CS and start clocking the data. When the data transfer is finished, clock is stopped and CS is deasserted.
Please notice that waiting for
while ( ( SPI_SLAVE_IsTxBusy (&SPI_SLAVE_0)), depending on the baudarate, it is possible that up to two words are still waiting to be shifted out (one in TBUF and one being shifted out in the DSU).
When using a proper SPI master, the master will stop the clock and deassert the CS when the total number of bytes are received.
Regards,
Jesus
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Mar 12, 2018
03:48 AM
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Mar 12, 2018
03:48 AM
Hi Jesus,
thanks for your Reply, but I thing you are wrong.
I modified the code that the send out of data is only every 2 ms.
So there is plenty on time to shift out 2 words for the XMC
Please take a look at the picture.
Yellow = clock into XMC
green = CS ( P5.3 & P.5.5 bridged )
purple = MISO
thanks for your Reply, but I thing you are wrong.
I modified the code that the send out of data is only every 2 ms.
So there is plenty on time to shift out 2 words for the XMC
Please take a look at the picture.
Yellow = clock into XMC
green = CS ( P5.3 & P.5.5 bridged )
purple = MISO
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Mar 12, 2018
03:55 AM
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Mar 12, 2018
03:55 AM
What is XMC doing ?
XMC should send out static data when chip select is going low
uint8_t Send_Data[] = {0x00,0xff,0xaa,0xff,0xaa,0xff,0xaa,0xff};
status = SPI_SLAVE_Transmit(&SPI_SLAVE_0, Send_Data, sizeof(Send_Data));
But, depending on the input frequency, sometime it is okay, sometimes it is not.
Some pictures which coniniusly running software:
Yellow = clock into XMC
green = CS ( P5.3 & P.5.5 bridged )
purple = MISO
This is looking goog.
This is looking bad.
This is not the way that the XMC isn't able to send out the data, but he is stopping after first 0xaa,
but why ?
Can you confirm this siutaion with your eval kit ?
Thanks and regards,
TSB
XMC should send out static data when chip select is going low
uint8_t Send_Data[] = {0x00,0xff,0xaa,0xff,0xaa,0xff,0xaa,0xff};
status = SPI_SLAVE_Transmit(&SPI_SLAVE_0, Send_Data, sizeof(Send_Data));
But, depending on the input frequency, sometime it is okay, sometimes it is not.
Some pictures which coniniusly running software:
Yellow = clock into XMC
green = CS ( P5.3 & P.5.5 bridged )
purple = MISO
This is looking goog.
This is looking bad.
This is not the way that the XMC isn't able to send out the data, but he is stopping after first 0xaa,
but why ?
Can you confirm this siutaion with your eval kit ?
Thanks and regards,
TSB