Dec 04, 2017
05:37 AM
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Dec 04, 2017
05:37 AM
I am trying to use the DMA (GPDMA0) to transfer 150 Bytes of data from a memory buffer to a USIC (USIC1_CH0) set to SPI mode on a XMC4500.
I have configured the USIC for SPI and I can use it to send data using Interrupts.
I have enabled the GPDMA0 and configured channel 3 for single block transfer:
The DLR is also configured:
The USIC is configured to generate a Service Request 1 on a transmit buffer Interrupt:
When I enable the DMA channel the source is read (8 Bytes) and the FIFO is not empty, but no data is written to the USIC. If I Trigger a transmit buffer Interrupt with the Software the first Byte of data is transmitted, but nothing more happens. I can see that the Service request is pending in the NVIC (ExtIRQ 91).
What do I need to do so that the DMA writes the rest of the data to the USIC?
I have configured the USIC for SPI and I can use it to send data using Interrupts.
I have enabled the GPDMA0 and configured channel 3 for single block transfer:
CTLL = 0x00100101
CFGL = 0x000008E0
CFGH = 0x00001804
Source and Destination Registers are correct
CFGL = 0x000008E0
CFGH = 0x00001804
Source and Destination Registers are correct
The DLR is also configured:
SRSEL0 = 0x0000X000
LNEN = 0x00000008
LNEN = 0x00000008
The USIC is configured to generate a Service Request 1 on a transmit buffer Interrupt:
CCR = 0x00002001
INPR = 0x00000010
INPR = 0x00000010
When I enable the DMA channel the source is read (8 Bytes) and the FIFO is not empty, but no data is written to the USIC. If I Trigger a transmit buffer Interrupt with the Software the first Byte of data is transmitted, but nothing more happens. I can see that the Service request is pending in the NVIC (ExtIRQ 91).
What do I need to do so that the DMA writes the rest of the data to the USIC?
- Tags:
- IFX
2 Replies
Dec 04, 2017
12:51 PM
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Dec 04, 2017
12:51 PM
Hi,
I would first disable FIFO and use just TX buffer, set HW handshake for DMA, first write to TBUF by SW manually and continuation will be by HW until length programed in CTLH_BLOCK_TS.
Check again all your settings in registers, also SRSEL0...
I do also this
// this will reset pending last request from previous transmission
DLR->LNEN &= ~((uint32_t)(DLR_LNEN_LN7_Msk));
DLR->LNEN |= ((uint32_t)(DLR_LNEN_LN7_Msk));
rum
I would first disable FIFO and use just TX buffer, set HW handshake for DMA, first write to TBUF by SW manually and continuation will be by HW until length programed in CTLH_BLOCK_TS.
Check again all your settings in registers, also SRSEL0...
I do also this
// this will reset pending last request from previous transmission
DLR->LNEN &= ~((uint32_t)(DLR_LNEN_LN7_Msk));
DLR->LNEN |= ((uint32_t)(DLR_LNEN_LN7_Msk));
rum
Dec 05, 2017
01:39 AM
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Dec 05, 2017
01:39 AM
I have managed to solve the problem.
I had the USIC interrupt set to "transmit buffer interrupt", this does not work. I have now changed to using the "transmit shift interrupt" and now it works as expected.
I am not quite sure why the buffer interrupt does not work. Does anyone have an idea?
I had the USIC interrupt set to "transmit buffer interrupt", this does not work. I have now changed to using the "transmit shift interrupt" and now it works as expected.
I am not quite sure why the buffer interrupt does not work. Does anyone have an idea?