XMC4800 EtherCAT Phy ICs

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User13774
Level 1
Level 1
Hi,

I am a new XMC user.

For a redesign of an application, build in the past with the Beckhoff ET1200 chip, I want to use the Ethercat interface of the XMC4800F144K2048AA.

  • The ET1200 has one only Ethercat PHy port, for IN. Is it possible to use the XMC4800 with only one Phy IC? If yes, is it possible to use in Dave 4.3.2 the ECAT_SSC App? What must be done, to make the software applicable?
  • On the Evaluationboard XMC4700_XMC4800_Relax_Kit_Series-UM-v01_02, the BCM5241XA1KMLG is used as Phy. I prefer to use the Micrel KSZ8081MNX. This IC is recomended by Beckhoff, but does it work in combination with the Infineon XMC4800?
  • The KSZ8081MNX has MII, there is also KSZ8081RNA with RMII interface. Is RMII also apllicable on the XMC4800?
  • Please can you also tell what software impact this have?



Regards,
Gerrard
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14 Replies
User12775
Level 5
Level 5
First solution authored First like received
Both MII and RMII interfaces are supported by XMC4x. But you maybe need to modify some driver code.
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User13774
Level 1
Level 1
Thank you aurixuser,
Do you have sample code of modified driver for RMII?
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User12775
Level 5
Level 5
First solution authored First like received

/**
* @brief GPIO configuration
* @param[in] interface Underlying network interface
**/

void xmc4800EthInitGpio(NetInterface *interface)
{
uint32_t temp;

//Configure ETH0.MDIO (P2.0), ETH0.RXD0A (P2.2) and ETH0.RXD1A (P2.3)
temp = PORT2->IOCR0;
temp &= ~(PORT2_IOCR0_PC0_Msk | PORT2_IOCR0_PC2_Msk | PORT2_IOCR0_PC3_Msk);
temp |= (0UL << PORT2_IOCR0_PC0_Pos) | (0UL << PORT2_IOCR0_PC2_Pos) | (0UL << PORT2_IOCR0_PC3_Pos);
PORT2->IOCR0 = temp;

//Configure ETH0.RXERA (P2.4), ETH0.TX_EN (P2.5) and ETH0.MDC (P2.7)
temp = PORT2->IOCR4;
temp &= ~(PORT2_IOCR4_PC4_Msk | PORT2_IOCR4_PC5_Msk | PORT2_IOCR4_PC7_Msk);
temp |= (0UL << PORT2_IOCR4_PC4_Pos) | (17UL << PORT2_IOCR4_PC5_Pos) | (17UL << PORT2_IOCR4_PC7_Pos);
PORT2->IOCR4 = temp;

//Configure ETH0.TXD0 (P2.8) and ETH0.TXD1 (P2.9)
temp = PORT2->IOCR8;
temp &= ~(PORT2_IOCR8_PC8_Msk | PORT2_IOCR8_PC9_Msk);
temp |= (17UL << PORT2_IOCR8_PC8_Pos) | (17UL << PORT2_IOCR8_PC9_Pos);
PORT2->IOCR8 = temp;

//Configure ETH0.CLK_RMIIC (P15.8) and ETH0.CRS_DVC (P15.9)
temp = PORT15->IOCR8;
temp &= ~(PORT15_IOCR8_PC8_Msk | PORT15_IOCR8_PC9_Msk);
temp |= (0UL << PORT15_IOCR8_PC8_Pos) | (0UL << PORT15_IOCR8_PC9_Pos);
PORT15->IOCR8 = temp;

//Assign ETH_MDIO (P2.0) to HW0
temp = PORT2->HWSEL & ~PORT2_HWSEL_HW0_Msk;
PORT2->HWSEL = temp | (1UL << PORT2_HWSEL_HW0_Pos);

//Select output driver strength for ETH0.TX_EN (P2.5)
temp = PORT2->PDR0;
temp &= ~PORT2_PDR0_PD5_Msk;
temp |= (0UL << PORT2_PDR0_PD5_Pos);
PORT2->PDR0 = temp;

//Select output driver strength for ETH0.TXD0 (P2.8) and ETH0.TXD1 (P2.9)
temp = PORT2->PDR1;
temp &= ~(PORT2_PDR1_PD8_Msk | PORT2_PDR1_PD9_Msk);
temp |= (0UL << PORT2_PDR1_PD8_Pos) | (0UL << PORT2_PDR1_PD9_Pos);
PORT2->PDR1 = temp;

//Use ETH0.CLK_RMIIC (P15.8) and ETH0.CRS_DVC (P15.9) as digital inputs
PORT15->PDISC &= ~(PORT15_PDISC_PDIS8_Msk | PORT15_PDISC_PDIS9_Msk);

//Select RMII operation mode
ETH0_CON->CON = ETH_CON_INFSEL_Msk | ETH_CON_MDIO_B | ETH_CON_RXER_A |
ETH_CON_CRS_DV_C | ETH_CON_CLK_RMII_C | ETH_CON_RXD1_A | ETH_CON_RXD0_A;
}
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User13774
Level 1
Level 1
I saw that the only the Ethernet port can handle RMII, not EtherCAT. So I have to use a Phy with MII.
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jferreira
Employee
Employee
10 sign-ins 5 sign-ins First like received
Hi,

RMII is not recommended by Beckhoff and XMC4800 does not support it as RMII PHYs include TX FIFO’s that increase the packet forwarding delay of an EtherCAT slave device as well as the jitter.
2877.attach

BTW, Have a look at the https://www.infineonforums.com/threads/3785-FAQ-for-XMC4800-EtherCAT

Regards,
Jesus
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User12775
Level 5
Level 5
First solution authored First like received
Sorry, I made mistake.

The ethernet(ETH) supports MII/RMII, the etherCAT(ECAT) doesn't.

In the reference manual:
15.1.1 ETH Core Features
• Supports 10/100-Mbit/s data transfer rates with the following PHY interfaces
– IEEE 802.3-compliant RMII/MII (default) interface to communicate with an external
Fast Ethernet PHY

EtherCAT slave devices with Ethernet Physical Layer usually support MII interfaces,some do also support the RMII interface. Since RMII PHYs include TX FIFO’s, they
increase the packet forwarding delay of an EtherCAT slave device as well as the jitter. RMII as a Ethernet Physical Layer is not supported by the XMC4[78]00 due to these
reasons.
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User15106
Level 1
Level 1
Hello
Did you get the XMC to work only with one PHY IC? We do not know where to make changes in the software.

Regards
Thomas
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jferreira
Employee
Employee
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Hi Thomas,

What do you mean by "with one PHY IC"?

Regards,
Jesus
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User15106
Level 1
Level 1
Hi Jesus,

since we only use the EtherCat In port, we want to save the EtherCat Out port on the PCB. We don't want to assemble the OUT-PHY.
What have we to do in software to disable the Output-EtherCat-Port in the EtherCat-Controller?

Thanks
Thomas
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MichaelIFX
Employee
Employee
50 replies posted 25 replies posted 10 replies posted
Hi Thomas,
On XMC43/48 we have two EtherCAT ports. For a regular EtherCAT device both ports are used.
If on the 2nd port another device is connected the device will send on P1/TX the frame (coming in from previous device on P0/RX of the 1st port) to the next device and receive on P1/RX (2nd port) the frame from the next device and forward it back to P0/TX(1st port) on the previous device.
Thereby the ethercat loop is closed.
If on the 2nd port no device is connected your device is the last device inside the EtherCAT ring. In this case on the 1st port RX should be directly loop-back to TX.
So also for this case the EtherCAT ring is closed!

As long as you have a PHY connected on the 2nd port, this is automatically controlled by the LINK_MII signal coming from PHY on the 2nd port.
If you have no PHY connected, the LINK_MII signal should be set to the correct level to close the 2nd port manually and enable loop-back on 1st port..

So the LINK_MII signal needs to be set to a correct static level.
The datasheet can be missunderstood this all can be done XMC-internally what is not exactly true. You have to enable LINK_MII on a pin and set the pin to the correct level.
For the other signals you can rely on the internal level.

See also hint inside errata-sheet: ECAT_CM.H001

Kind Regards

Michael
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User16372
Level 1
Level 1
Hello,

I have a code working nicely with only one ecat port. The P0.
In order to get it work had to assign the P1_LINK_MII to a free input and enable internal pull-up. The same for the rest of the signals of P1. I assigned them to pins and then internally pulled them down.
So If I understood correctly from the datasheet, I have to use the Internal levels for all the signals except P1_LINK_MII.

For example for the signal P1_RX_DV does that mean that I have to select 3U as 0U,1U,2U are assigned already to a Pin?

typedef enum XMC_ECAT_PORT1_CTRL_RX_DV
{
XMC_ECAT_PORT1_CTRL_RX_DV_P0_9 = 0U, /**< RX_DVA Receive data valid */
XMC_ECAT_PORT1_CTRL_RX_DV_P14_15 = 1U, /**< RX_DVB Receive data valid */
XMC_ECAT_PORT1_CTRL_RX_DV_P8_11 = 2U, /**< RX_DVC Receive data valid */

} XMC_ECAT_PORT1_CTRL_RX_DV_t;
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jferreira
Employee
Employee
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Hi,

Yes, assigning it to 3 would be fine, from the reference manual,
If an ESC MII interface is not used, input pins like LINK_MII has to be tied to the logic
value high which indicates no link. RX_CLK, RXD, RX_ER, and especially RX_DV have
to be tied to GND. For this purpose you can select a input position in register
ECAT0_CONPx of these signals which are not connected to a pin on the XMC4[78]00.



Regards,
Jesus
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User16372
Level 1
Level 1
Hello,

Thank you very much for the reply. Do you think would make sense to include this 3U option in the Enum as followed


typedef enum XMC_ECAT_PORT1_CTRL_RX_DV
{
XMC_ECAT_PORT1_CTRL_RX_DV_P0_9 = 0U, /**< RX_DVA Receive data valid */
XMC_ECAT_PORT1_CTRL_RX_DV_P14_15 = 1U, /**< RX_DVB Receive data valid */
XMC_ECAT_PORT1_CTRL_RX_DV_P8_11 = 2U, /**< RX_DVC Receive data valid */
XMC_ECAT_PORT1_CTRL_RX_DV_PULL_DOWN = 3U, /**< RX_DVC Receive data valid */
} XMC_ECAT_PORT1_CTRL_RX_DV_t;
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jferreira
Employee
Employee
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Hi,

Yes, we have already added it to the next XMCLib release.

Regards,
Jesus
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