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Thread: Problem with the FIFO using USIC on XC2365A

  1. #1
    Beginner Beginner AES is on a distinguished road
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    Problem with the FIFO using USIC on XC2365A

    Hello all,

    I got a unusual error when I use the FIFO. The Configuration is done with DAVE.

    Received FIFO using(U0C0_OUTRL)
    Transmit FIFO using (U0C0_IN00)

    Received and Transmit using different memory location.

    In the case below I forced the Transmitter to send only 0x55 (U0C0_IN00=0x55; ) but the results are confusing me.
    Click image for larger version

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    I send via a tool data's per RS232 interface. The Received data I saved into a different signal but I will do nothing more with it. The transmission as I said, is force to 0x55.

    The expected Output should only be 0x55, for the "READ" in the picture. But as you can see, I also get different data's, but where are these data's coming from, when I force the output to 0x55?.

    Has some one an idea why I get this

    Thanks for your Help

  2. #2
    Beginner Beginner Isnochys79 is on a distinguished road
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    Did you check the datasheet for XC2365A? Check here - https://www.icrfq.com/part/2402587-X...RABKXUMA1.html for XC2365A manufacturer (Infineon) datasheet. I think you can get an idea.

  3. #3
    Beginner Beginner AES is on a distinguished road
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    Update: It looks like that there is a problem with the transmit. I done the following to find out why I got unexpected data.

    Code:
    while (U0C0_TRBSRH_TBFLVL < 15)
       {
        	  U0C0_IN00=RS_OUT[index_out++];
        	  TX_RX_CHECK_COUNT[1]++;
       }
       TX_RX_CHECK_BUFF_LVL[1]=U0C0_TRBSRH_TBFLVL;
    What I expect with the loop:
    TX_RX_CHECK_COUNT[1] shall be equal to U0C0_TRBSRH_TBFLVL : When Debugging the software the counter and the TBFLVL are equal every time.
    But when I run the software for few seconds "Realtime" the counter and the TBFLVL are not equal.

    Update :2
    Now I was able to trace the "U0C0_TRBSRH_TBFLVL" and that's what happens:


    U0C0_TRBSRH_TBFLVL = 0 : TX_RX_CHECK_COUNT[1]=0
    U0C0_TRBSRH_TBFLVL = 1 : TX_RX_CHECK_COUNT[1]=1
    U0C0_TRBSRH_TBFLVL = 2 : TX_RX_CHECK_COUNT[1]=2
    U0C0_TRBSRH_TBFLVL = 3 : TX_RX_CHECK_COUNT[1]=3
    U0C0_TRBSRH_TBFLVL = 4 : TX_RX_CHECK_COUNT[1]=4
    U0C0_TRBSRH_TBFLVL = 5 : TX_RX_CHECK_COUNT[1]=5
    U0C0_TRBSRH_TBFLVL = 6 : TX_RX_CHECK_COUNT[1]=6
    U0C0_TRBSRH_TBFLVL = 8 : TX_RX_CHECK_COUNT[1]=7
    U0C0_TRBSRH_TBFLVL = A : TX_RX_CHECK_COUNT[1]=8
    U0C0_TRBSRH_TBFLVL = E : TX_RX_CHECK_COUNT[1]=9
    U0C0_TRBSRH_TBFLVL = 10 : TX_RX_CHECK_COUNT[1]=A

    Question is why the TBFLVL is increasing when I did not write on it?

    Did anyone got maybe a similar error/problem?
    Last edited by AES; Nov 7th, 2017 at 07:17 AM.

  4. #4
    Beginner Beginner AES is on a distinguished road
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    Hello,
    is it possible that the error comes from a wrong configuration?
    Here are the Configuration, most of these comes from D.A.V.E.

    The Issue is really confusing

    Thanks to all who try to help me

    Code:
    void RS232_Init(void)
    {
        ScuRegDisableProtection();
        /* load U0C0 kernel state configuration register */
        U0C0_KSCFG     =  3;
        /* two cycles delay */
        __nop();
        __nop();
        ScuRegEnableProtection();
    
        /* U0C0 = idle */
        U0C0_CCR       =  0x0000;
    
        /* ----- Initialize U0C0 ----- */
    
        /*   -----------------------------------------------------------------------
             Configuration of the U0C0 Fractional Divider:
             -----------------------------------------------------------------------
             - The Fractional divider is selected DM=2
             - The step value STEP = 786
        */
        /* load U0C0 fractional divider register 61.406MHz at 80MHz fsys*/
        U0C0_FDRL = 0;
        U0C0_FDRL_DM   =  2;
        U0C0_FDRL_STEP =  0x0312;
    
        /*  -----------------------------------------------------------------------
             Configuration of the U0C0 Baudrate Generator:
             -----------------------------------------------------------------------
             - The selected BaudRate is 19,200 kbaud (PDIV=99)
             - The selected BaudRate is 9,600 kbaud (PDIV=199)
             - The PreDivider for CTQ, PCTQ = 1
             - The Denominator for CTQ, DCTQ = 15
             - The Divider factor PDIV = 99
    	*/
        U0C0_BRGL = 0;
        U0C0_BRGL_DCTQ = 15;
        U0C0_BRGL_PCTQ =  1;
        U0C0_BRGH = 0;
        U0C0_BRGH_PDIV = 99;
    
        /*  -----------------------------------------------------------------------
            Configuration of the U0C0 Input Control Register 0:
            -----------------------------------------------------------------------
            - The data input DX0D is selected for pin - P7.4
    	*/
        U0C0_DX0CR = 0;
        U0C0_DX0CR_DSEL     = 3;         // load U0C0 input control register(Data)
        U0C0_DX0CR_DFEN     = 1;
    
        /*   -----------------------------------------------------------------------
             Configuration of the U0C0 Interrupt Node Pointer Register:
             Receive Buffer Interrupt : SR1
             Protocol Interrupt: SR1
             Transmit Buffer Interrupt: SR0
             -----------------------------------------------------------------------
        */
        U0C0_INPRL = 0;
        U0C0_INPRL_RINP = 1;
        U0C0_INPRL_TBINP = 0;
        U0C0_INPRH_PINP = 1;
    
        /*   -----------------------------------------------------------------------
             Configuration of the U0C0 Shift Control:
             -----------------------------------------------------------------------
             - SCTRL_SDIR = 0, - Transmit/Receive shift LSB first
             - SCTRL_TRM = 1,  - The shift control signal is considered active if it is at 1-level, allow data transfers.
             - SCTRL_PDL = 1,  - The passive data level is 1
             - SCTRH_WLE = 7,  - The word length is 7 (8 data bits)
             - SCTRH_FLE = 7,  - The frame length is 7
        */
        U0C0_SCTRL = 0;
        U0C0_SCTRL_TRM = 1;
        U0C0_SCTRL_PDL = 1;
    
        U0C0_SCTRH = 0;
        U0C0_SCTRH_WLE = 7;
        U0C0_SCTRH_FLE = 7;
    
        /*   -----------------------------------------------------------------------
             Configuration of the U0C0 Transmit Control/Status Register:
             -----------------------------------------------------------------------
             - TCSRL_TDEN = 1,  - TBUF data transmission starts if TDV = 1
             - TCSRL_TDSSM = 1, - TBUF data single shot mode: TBUF data transferred only once
        */
        U0C0_TCSRL     =  0;
        U0C0_TCSRL_TDEN = 1;
        U0C0_TCSRL_TDSSM = 1;
        U0C0_TCSRH     =  0x0000;
    
        /*   -----------------------------------------------------------------------
             Configuration of the U0C0 Protocol Control Register:
             -----------------------------------------------------------------------
             - Sample Mode (SMD) = 1
             - 1 Stop bit is selected
             - Sample Point (SP) = 7
             - Pulse Length (PL) = 0
             - Break enabled
        */
    	U0C0_PCRL =0;
        U0C0_PCRL_SBIEN = 1;
        U0C0_PCRL_SP = 7;
        U0C0_PCRL_SMD = 1;
        U0C0_PCRH = 0x0000;
    
    
    	/* Transmit: ILVL=4, IE=1, GLVL=1 */
        U0C0_0IC = CreateInterruptControl(0,0,1,4,1);
    
    	/* Receive: ILVL=4, IE=1, GLVL=0 */
        U0C0_1IC = CreateInterruptControl(0,0,1,4,0);
    
        /*   -----------------------------------------------------------------------
             Configuration of U0C0 FIFO:
             -----------------------------------------------------------------------
             -----------------------------------------------------------------------
             Configuration of U0C0 Transmitter Buffer Control Register:
             -----------------------------------------------------------------------
             - Transmit FIFO buffer contains 16 entries
             - Transmit FIFO buffer starts at Data Pointer 0
             - Limit for transmit FIFO interrupt generation is 0
             - Standard Transmit buffer interrupt is (enabled) disabled
        */
        U0C0_TBCTRL    =  0;
        U0C0_TBCTRH    =  0;
        U0C0_TBCTRH_STBIEN = 1;
        U0C0_TBCTRH_SIZE = 4;
        /*   -----------------------------------------------------------------------
             Configuration of U0C0 Receiver Buffer Control Register:
             -----------------------------------------------------------------------
             - Receive FIFO buffer contains 16 entries
             - Receive FIFO buffer starts at Data Pointer 16
             - Limit for receive FIFO interrupt generation is 1
             - Filling level mode is selected
             - Standard Receive buffer interrupt is disabled (enabled)
        */
        U0C0_RBCTRL = 0;
        U0C0_RBCTRL_DPTR = 16;
        U0C0_RBCTRL_LIMIT = 1;
        U0C0_RBCTRH    =  0;
        U0C0_RBCTRH_SRBIEN = 0;
        U0C0_RBCTRH_SIZE = 4;
        U0C0_RBCTRH_SRBINP = 1;     /* SR1 */
        /*   -----------------------------------------------------------------------
             Configuration of the used U0C0 Port Pins:
             -----------------------------------------------------------------------
        */
    
        P7_IOCR04 = 0x0020;  //InputDirect-PullUp
        P7_IOCR03 = 0x00B0;  //Output-PushPullAlt3
    
        /* U0C0 = ASC*/
        U0C0_CCR_MODE = 2;
    
        /* Receive Interrupt enable */
        U0C0_CCR_RIEN = 1;
    
        /* Transmit Interrupt enable */
        U0C0_CCR_TBIEN = 1;
    
    }
    Last edited by AES; Nov 8th, 2017 at 07:36 AM.

  5. #5
    Beginner Beginner AES is on a distinguished road
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    After many analysis the problem is a timing issue. When I add a wait after the transmit then I got no FIFO corruptions. With the Configuration above I should wait around 6,666ms for the next transmit to be sure that the FIFO was cleared.

  6. #6
    Beginner Beginner reviews is on a distinguished road
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    Did you check the datasheet for XC2365A?

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