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Thread: Ethernet issue with TC 279x (SMI/MDIO interface)

  1. #1
    New Member New Member Cell is on a distinguished road
    Join Date
    Jun 2017

    Ethernet issue with TC 279x (SMI/MDIO interface)

    Good morning, I am working on a board equipped with a
    Tricore processor (Aurix TC297B version).

    The board contains also a chipset that provides the
    functionalities of Ethernet switch and other components.

    I need that the Aurix processor communicates to the Ethernet
    chipset using the SMI/MDIO interface, in order to perform
    Ethernet configuration.

    Unfortunately, in the last weeks I was unable to obtain a
    working communication between the processor and the
    Ethernet chipset.

    In fact, despite I configured the Aurix registers for SMI/MDIO
    access, when I try to read one of the 32 registers that are made
    available by the SMI interface, the value returned by the
    read_SMI() routine is ALWAYS 0xFFFF.

    The result is the same trying to address the Ethernet chipset
    using each of the 32 PHY slave IDs available on the SMI bus

    (in my tests, I assumed that Aurix automatically configures
    itself as the master device in the SMI/MDIO bus).

    I performed the following steps:

    - The pin P12.0 was set in order to use the ETHRXCLKC
    signal. Following the Aurix TC297B manual (tc29xB_um_v1.3),
    this can be obtained using the settings:

    ETH_GPCTL.ALTI1 = 10b (i.e. 02h)
    P12_IOCR0.PC0 = 0XXXXb (I used 0Fh
    i.e. 01111b)

    (page 1214/13-128 of the Aurix TC297B manual)

    - The pin P12.1 was set in order to use the ETHMDIOC signal.
    Following the Aurix TC297B manual, this can be obtained
    using the following settings:

    ETH_GPCTL.ALTI0 = 10b (i.e. 02h)
    P12_IOCR0.PC1 = 0XXXb (I used 07h
    i.e. 0111b)

    (page 5313/34-463 of the Aurix TC297B manual)

    I have not used the macros provided by Infineon for
    modifying the registers.

    I prefer to directly write the routines needed to change
    the target bit fields.

    In order to modify the P12_IOCR0 register, I proceeded
    in the following way.

    I read that the register address space dedicated to the
    P12 port starts at the address F003B200h
    (page 1094/13-8 of the manual).

    I added the offset 0010h for addressing IOCR0 control
    register (page 1095/13-9 of the manual), thus obtaining
    the address F003B210h.

    Next, I performed the changes on the bit fields dedicated
    to PC0 and PC1 at the address F003B210h.

    Is this procedure correct ? Perhaps some steps in Ethernet
    SMI interface configuration are missing ?

    Thanks in advance for your help.

  2. #2
    Beginner Beginner audiolines is on a distinguished road
    Join Date
    May 2018
    Hi, Were you able to get any progress on this?

    Any ideas on how to solve this? Is it working for you?

  3. #3
    New Member New Member
    Infineon Employee
    Infineon Employee
    MoD is on a distinguished road
    Join Date
    Feb 2012
    you must set the P12.0 to ETHMDC. P12.0 is the clock and P12.1 is the data line for MAC I/O. I expect that you will use this pins with this functionality.
    Please see also table 34-53. You must set P12_IOCR0.PC0 = 10110B then you get an output clock and you can access your PHY.
    The views expressed here are my personal opinions, have not been reviewed or authorized by Infineon and do not necessarily represent the views of Infineon.

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