infineon4engineers Facebook

infineon@google+ Google+

infineon@linkedin linkedin

infineon4engi@twitter twitter

infineon@youtube youtube

Dave

+ Reply to Thread
Page 1 of 2 1 2 LastLast
Results 1 to 10 of 11

Thread: XMC1400 - Running from the standby clock (32kHz DCO2) after deep sleep wake-up

  1. #1
    Beginner Beginner xmc-12345 is on a distinguished road
    Join Date
    Aug 2017
    Posts
    10
    Points
    110

    XMC1400 - Running from the standby clock (32kHz DCO2) after deep sleep wake-up

    Hi,

    As far as I understand, when going to deep sleep mode the DCO1(96MHz oscillator) is disabled and then MCLK/PCLK is running from the standby clock (32kHz oscillator DCO2).
    When the device wakes up from the deep sleep (e.g. via SysTick interrupt) I see that the MCLK/PCLK is switched back automatically to DCO1.

    Is there an option to configure the device in such a way that after wake-up form deep sleep it:
    - keeps DCO1(96MHz) off
    AND
    - runs from the standby clock (32kHz DCO2)?

    Thanks.

  2. #2
    Intermediate Intermediate aurixuser is on a distinguished road
    Join Date
    Jan 2017
    Location
    China
    Posts
    155
    Points
    3100
    As illustrated by the reference manual, it is possible.
    Click image for larger version

Name:	cgu_xmc1.png
Views:	3
Size:	68.1 KB
ID:	3075

  3. #3
    Beginner Beginner xmc-12345 is on a distinguished road
    Join Date
    Aug 2017
    Posts
    10
    Points
    110
    Hi,

    Thanks for the feedback.
    I know the diagram and it is clear there is a path to feed the DCO2 clock to MCLK/PCLK (as it actually happens during deep sleep mode according to the Reference Manual).
    What I did not manage to clarify is the register or register set that have to be modified to:
    Set DCO2 as source clock for the MCLK/PCLK domain during normal operation
    Is that even possible?
    As far as I understand from section 14.5.2 Clock System and Control (attached below), seems like it is not, but that is actually what I would like to clarify in this thread...

    By normal operation in the text above I mean:
    Setting DCO2 as source for MCLK/PCLK without the need of generating any of the oscillator failure events:
    • 14.5.2.2 Loss of DCO1 Clock Detection and Recovery
    • 14.5.2.5 Loss of external OSC_HP Clock Detection and Recovery
    • etc...

    Thanks in advance for your support.

    14.5.2 Clock System and Control
    Figure 14-4 shows the block diagram of the clock system in XMC1400. It consists of two
    on-chip oscillators (DCO1 1) with synchronisation unit and DCO2), 2 oscillators pad
    (OSC_HP and OSC_LP to drive external clock), a doubler and a clock control unit
    (CCU). DCO1 has a clock output (dco1_clk), running at 48MHz. DCO2 is used to
    generate the standby clock running at 32kHz.
    The main clock, MCLK, and fast peripherial clock, PCLK, are generated from DCLK
    (output of the doubler clock). Input to DCLK can be selected using bit
    CLKCR1.DCLKSEL to be either from the DCO1 clock source or the external clock
    source via the OSC_HP oscillator.

  4. #4
    Beginner Beginner xmc-12345 is on a distinguished road
    Join Date
    Aug 2017
    Posts
    10
    Points
    110
    Hi,

    Could you please help me pointing out e.g.: the register or set of registers to:
    Set DCO2 as clock source for MCLK/PCLK
    Is that even possible under normal operation (without generating a loss clock situation)?

    Thanks!
    Last edited by xmc-12345; Aug 9th, 2017 at 11:53 AM.

  5. #5
    Intermediate Intermediate aurixuser is on a distinguished road
    Join Date
    Jan 2017
    Location
    China
    Posts
    155
    Points
    3100
    I just get the conclusion from the user manual. I have not done the register setting in my application. Maybe you need to dig the user manual for the detail.

  6. #6
    Beginner Beginner xmc-12345 is on a distinguished road
    Join Date
    Aug 2017
    Posts
    10
    Points
    110
    Hi,

    I already check all clock related sections of the reference manual without success.
    My conclusion is that setting DCO2 as clock source for MCLK/PCLK under normal operation is simply not possible, but would like to have a confirmation e.g.: from an Infineon employee to stop digging and investing time in this topic.

    BR.

  7. #7

    Infineon Employee
    Infineon Employee
    jferreira will become famous soon enough
    Join Date
    Oct 2012
    Posts
    303
    Hi,

    It is not possible to use DCO2 as clock source for MCLK/PCLK in normal mode.
    What about if you ramp down DCO1 before entering deep sleep mode?

    Regards,
    Jesus
    The views expressed here are my personal opinions, have not been reviewed or authorized by Infineon and do not necessarily represent the views of Infineon.

  8. #8
    Beginner Beginner xmc-12345 is on a distinguished road
    Join Date
    Aug 2017
    Posts
    10
    Points
    110
    Hi Jesus,

    Thanks for your answer.

    Ramping down DCO1 is our current approach, but the following topic is open:
    Which is the maximum MCLK/PCLK frequency allowed before going to deep sleep mode?
    I started a new thread for it few days ago:
    https://www.infineonforums.com/threa...eep-sleep-mode
    Could you please help us to clarify it?

    BR.

  9. #9

    Infineon Employee
    Infineon Employee
    jferreira will become famous soon enough
    Join Date
    Oct 2012
    Posts
    303
    Hi,

    The maximum recommended is 4 times the frequency of DCO2 to prevent a sudden load change that could cause a brownout reset when entering sleep or deep sleep mode.
    Actually I would go down to 32KHz.

    Regards,
    Jesus
    The views expressed here are my personal opinions, have not been reviewed or authorized by Infineon and do not necessarily represent the views of Infineon.

  10. #10
    Beginner Beginner xmc-12345 is on a distinguished road
    Join Date
    Aug 2017
    Posts
    10
    Points
    110
    Hi Jesus,

    According to:
    Table 14-4 PCLK and MCLK frequency range
    The frequency range for MCLK when using DCO1 as clock source is: 188kHz - 48MHz

    So, even when using the maximum values for IDIV and FDIV, the minimum operating frequency of MCLK (with DCO1) is ~188kHz which is out of the range recommended in the previous reply:
    The maximum recommended is 4 times the frequency of DCO2 to prevent a sudden load change that could cause a brownout reset when entering sleep or deep sleep mode.
    Perhaps I am missing something here, or miscalculating the frequency range for MCLK when using DCO1 as clock source, but I would find very restrictive if DCO1 cannot be used as as clock source for MCLK when going to sleep/deep-sleep mode.

    Could you please help me to clarify the following topics:
    1. Is there a risk of producing brownout resets when entering sleep or deep-sleep mode with MCLK=~188kHz?
    2. Does it mean that using DCO1 as clock source for MCLK IS NOT compatible with sleep/deep-sleep mode?

    Thank you and BR

+ Reply to Thread
Disclaimer

All content and materials on this site are provided “as is“. Infineon makes no warranties or representations with regard to this content and these materials of any kind, whether express or implied, including without limitation, warranties or representations of merchantability, fitness for a particular purpose, title and non-infringement of any third party intellectual property right. No license, whether express or implied, is granted by Infineon. Use of the information on this site may require a license from a third party, or a license from Infineon.


Infineon accepts no liability for the content and materials on this site being accurate, complete or up- to-date or for the contents of external links. Infineon distances itself expressly from the contents of the linked pages, over the structure of which Infineon has no control.


Content on this site may contain or be subject to specific guidelines or limitations on use. All postings and use of the content on this site are subject to the Usage Terms of the site; third parties using this content agree to abide by any limitations or guidelines and to comply with the Usage Terms of this site. Infineon reserves the right to make corrections, deletions, modifications, enhancements, improvements and other changes to the content and materials, its products, programs and services at any time or to move or discontinue any content, products, programs, or services without notice.