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Apr 20, 2017
05:26 AM
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Apr 20, 2017
05:26 AM
Hi,
I have generated a project to obtain high sampling rate of VADC using XMC4500-F100x1024 Relax Lite Kit. But the output graph I generated seems like the sampling is not good enough..Can anybody tell me
what I did wrong in the VADC settings. I am hereby attaching my VADC settings as well as some screenshots of the output graph.
pics:-
VADC Settings:-
Thanks in advance...
I have generated a project to obtain high sampling rate of VADC using XMC4500-F100x1024 Relax Lite Kit. But the output graph I generated seems like the sampling is not good enough..Can anybody tell me
what I did wrong in the VADC settings. I am hereby attaching my VADC settings as well as some screenshots of the output graph.
pics:-
VADC Settings:-
Thanks in advance...
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3 Replies
Apr 22, 2017
02:05 AM
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Apr 22, 2017
02:05 AM
Which channel is which signal?
For example, what is the original signal shape?
For example, what is the original signal shape?
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Apr 23, 2017
09:49 PM
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Apr 23, 2017
09:49 PM
Hi Aurixuser,
CH2 is actually what I am moitoring..Rightnow sine wave signal is connected to that channel..the frequencies i mentioned in the pictures are what i connected from a signal generator to the corresponding
VADC pin..Actually, if i connect the input from functionn generator to any four VADC channels that i am using will give me the same output graphs..From my observation what i can see is while using
four stage FIFO in VADC and if i enable result event after the 4th conversion , all the four result registers contains the same result even though the input signal frequency is too high.
Thanks in advance...
CH2 is actually what I am moitoring..Rightnow sine wave signal is connected to that channel..the frequencies i mentioned in the pictures are what i connected from a signal generator to the corresponding
VADC pin..Actually, if i connect the input from functionn generator to any four VADC channels that i am using will give me the same output graphs..From my observation what i can see is while using
four stage FIFO in VADC and if i enable result event after the 4th conversion , all the four result registers contains the same result even though the input signal frequency is too high.
Thanks in advance...
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Apr 24, 2017
12:35 PM
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Apr 24, 2017
12:35 PM