Apr 03, 2017
04:31 AM
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Apr 03, 2017
04:31 AM
Dear all,
I'm evaluation to use one of the XMC microcontroller for a measurement setup which will employs several ADC, and DACs.
I have the requirement to have a simultaneous control of all, and at the same time load and save the values into a volatile ram (or whatever).
The current solution employs a classic Arduino Leonardo, which with the series strategy needs 36µs to control all the devices.
From my experience, for such task I should use a FPGA or equivalent, however this solution would increase the complexity of the control system.
I would like to understand if one of the XMC available could control simultaneously different SPI channels, with different configurations (frequency, and mode).
And then if it would be possible to interface it with an external RAM in order to increase the small (~300kb) ram available.
Thanks.
I'm evaluation to use one of the XMC microcontroller for a measurement setup which will employs several ADC, and DACs.
I have the requirement to have a simultaneous control of all, and at the same time load and save the values into a volatile ram (or whatever).
The current solution employs a classic Arduino Leonardo, which with the series strategy needs 36µs to control all the devices.
From my experience, for such task I should use a FPGA or equivalent, however this solution would increase the complexity of the control system.
I would like to understand if one of the XMC available could control simultaneously different SPI channels, with different configurations (frequency, and mode).
And then if it would be possible to interface it with an external RAM in order to increase the small (~300kb) ram available.
Thanks.
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5 Replies
Apr 03, 2017
06:11 AM
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Apr 03, 2017
06:11 AM
How do you control a volatile ram with an Arduino Leonardo?
Do you mean the internal RAM?
And how do you mean "simultaneous "?
All the XMC micro controllers are single-core, so you need to control the ADC/DACs one by one.
Do you mean the internal RAM?
And how do you mean "simultaneous "?
All the XMC micro controllers are single-core, so you need to control the ADC/DACs one by one.
Apr 03, 2017
07:36 AM
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Apr 03, 2017
07:36 AM
Hi,
Thanks for the reply.
In order to "control" the internal Leornardo's RAM (ATmega32u4), right now I just pre-allocate the space I need through several commands.
I copied what I am currently using:
One for each variable.
And then for every device, I need to configure the SPI channel to the right configuration (speed, and mode), then I can transfer the data.
This allows me to have space for something like 200 samples, due to the small amount of ram available on board (2.5 KB)
For simultaneous, I mean that I'm going to send the clocks to all the ICs, and at the same time transmitting/receiving data to all together simultaneously.
I tried to implement a manual control of different pin (with rise up, and falling down phase of the CLK signal) but the process control of the pin through register is quite slow, let's say not optimized like the dedicated SPI transceiver.
I cannot reach more than 4MHz of clock, which moreover has a not constant duty cycle.
To implement this function in a FPGA results be quite simple, but it will increase the complexity of the system.
For this reason, I though that due to the DMA channel inside the XMC, it would be possible to give an address from where to read/write automatically, and then to synchronize just the clock.
Thanks for the reply.
In order to "control" the internal Leornardo's RAM (ATmega32u4), right now I just pre-allocate the space I need through several commands.
I copied what I am currently using:
// data memory
#define MEMORYDIMENSION 200
unsigned long ADCx [MEMORYDIMENSION];
unsigned long DACy [MEMORYDIMENSION];
One for each variable.
And then for every device, I need to configure the SPI channel to the right configuration (speed, and mode), then I can transfer the data.
This allows me to have space for something like 200 samples, due to the small amount of ram available on board (2.5 KB)
For simultaneous, I mean that I'm going to send the clocks to all the ICs, and at the same time transmitting/receiving data to all together simultaneously.
I tried to implement a manual control of different pin (with rise up, and falling down phase of the CLK signal) but the process control of the pin through register is quite slow, let's say not optimized like the dedicated SPI transceiver.
I cannot reach more than 4MHz of clock, which moreover has a not constant duty cycle.
To implement this function in a FPGA results be quite simple, but it will increase the complexity of the system.
For this reason, I though that due to the DMA channel inside the XMC, it would be possible to give an address from where to read/write automatically, and then to synchronize just the clock.
Apr 03, 2017
10:04 AM
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Apr 03, 2017
10:04 AM
To my knowledge, the DMA channels are only designed to transfer from one periphery to memory and vice vera.
Your problem is "simultaneously read", But the GPIO style common clock is slower than you need, right?
My suggestion: Try to run the code in SRAM. It will be much faster because the Flash has wait cycle.
Which XMC do you plan to use(XMC45?).
Your problem is "simultaneously read", But the GPIO style common clock is slower than you need, right?
My suggestion: Try to run the code in SRAM. It will be much faster because the Flash has wait cycle.
Which XMC do you plan to use(XMC45?).
Apr 04, 2017
12:21 AM
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Apr 04, 2017
12:21 AM
I was oriented for the XMC with the larger amount of RAM, thus the 47 or the 48 series.
If I would control the GPIO manually, which is the maximum frequency which could be reachable?
In order to control all the devices at full speed I should be able to generate clocks at 50MHz.
If I would control the GPIO manually, which is the maximum frequency which could be reachable?
In order to control all the devices at full speed I should be able to generate clocks at 50MHz.
Apr 05, 2017
01:32 AM
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Apr 05, 2017
01:32 AM
With the XMC47/48, the system clock is up to 144MHz.
If you need a GPIO toggle style clock of 50MHz, you need to toggle the pin at 100MHz.
And you still need to shift values between these toggling.
I have not tested it, but this approach seems infeasible.
If you need a GPIO toggle style clock of 50MHz, you need to toggle the pin at 100MHz.
And you still need to shift values between these toggling.
I have not tested it, but this approach seems infeasible.