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Mar 27, 2017
07:32 AM
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Mar 27, 2017
07:32 AM
Hi,
We want to generate a PWM output signal on one channel without CPU interaction. It can be CCU40 or CCU80, we have no preference.
The setup is:
1) Timer module generates pulses at a certain interval
2) DMA module is triggered by the pulses generated in (1). On every pulse, it transfers a 16-bit value to the PWM period match register.
3) The PWM module is running, but it does not update the period match register.
The problem is the shadow transferring mechanism. I can successfully update the PWM period match register with DMA, but according to the datasheet I also need to manually write to the shadow transfer enable register with the CPU.
Is it possible to trigger a shadow transfer without the need for CPU interaction?
I see that there is a connection between the POSIF module and the shadow transfer enable pin (hardware). Can I use this functionality somehow to address my problem?
The purpose is to play an audio file without CPU interaction.
Thanks
Rickard
We want to generate a PWM output signal on one channel without CPU interaction. It can be CCU40 or CCU80, we have no preference.
The setup is:
1) Timer module generates pulses at a certain interval
2) DMA module is triggered by the pulses generated in (1). On every pulse, it transfers a 16-bit value to the PWM period match register.
3) The PWM module is running, but it does not update the period match register.
The problem is the shadow transferring mechanism. I can successfully update the PWM period match register with DMA, but according to the datasheet I also need to manually write to the shadow transfer enable register with the CPU.
Is it possible to trigger a shadow transfer without the need for CPU interaction?
I see that there is a connection between the POSIF module and the shadow transfer enable pin (hardware). Can I use this functionality somehow to address my problem?
The purpose is to play an audio file without CPU interaction.
Thanks
Rickard
9 Replies
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Mar 29, 2017
12:11 AM
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Mar 29, 2017
12:11 AM
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Mar 29, 2017
06:27 AM
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Mar 29, 2017
06:27 AM
Thanks, that is just what I'm looking for!
However I still have a problem with memory size. In your example - and also in other DMA <-> peripheral devices - the buffer is using 4 byte (uint32_t) values. The peripheral destination value I want to set is only 16 bits, so there is no need for the extra 2 bytes. We need to save RAM so we would like to only use 16-bit values in the buffer.
I have tried setting the transfer width of both source and destionation to XMC_DMA_CH_TRANSFER_WIDTH_16 in the DMA, but it does not work.
I have also tried setting the transfer width of source to XMC_DMA_CH_TRANSFER_WIDTH_16, and destination to XMC_DMA_CH_TRANSFER_WIDTH_32, but it doesn't work either.
Is there a way to perform generic DMA transfer from 16-bit values to 32-bit registers?
Thanks
Rickard
However I still have a problem with memory size. In your example - and also in other DMA <-> peripheral devices - the buffer is using 4 byte (uint32_t) values. The peripheral destination value I want to set is only 16 bits, so there is no need for the extra 2 bytes. We need to save RAM so we would like to only use 16-bit values in the buffer.
I have tried setting the transfer width of both source and destionation to XMC_DMA_CH_TRANSFER_WIDTH_16 in the DMA, but it does not work.
I have also tried setting the transfer width of source to XMC_DMA_CH_TRANSFER_WIDTH_16, and destination to XMC_DMA_CH_TRANSFER_WIDTH_32, but it doesn't work either.
Is there a way to perform generic DMA transfer from 16-bit values to 32-bit registers?
Thanks
Rickard
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Mar 30, 2017
07:04 AM
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Mar 30, 2017
07:04 AM
Hi again,
The sample code that you provided works as intended. However there are still some features that are not included in the sample code. I've tried to get them to work, but I have not had any success yet.
1) As in my previous post, I need to save RAM so I cannot use 32 bit buffers for the DMA transfers to the CCU unit. I need to setup the DMA to read 8-bit (or 16-bit) values and write them to the 32-bit register of the CCU Compare register.
Instead of uint32_t duty_cycles[2][48], I would like uint8_t duty_cycles[2][48].
2) I need to generate an interrupt (to ISR) whenever a block in the linked list has been completed. I tried using the XMC_DMA_CH_EnableEvent() and XMC_DMA_CH_SetEventHandler() functions, but I still do not get into my ISR.
Thanks
Rickard
The sample code that you provided works as intended. However there are still some features that are not included in the sample code. I've tried to get them to work, but I have not had any success yet.
1) As in my previous post, I need to save RAM so I cannot use 32 bit buffers for the DMA transfers to the CCU unit. I need to setup the DMA to read 8-bit (or 16-bit) values and write them to the 32-bit register of the CCU Compare register.
Instead of uint32_t duty_cycles[2][48], I would like uint8_t duty_cycles[2][48].
2) I need to generate an interrupt (to ISR) whenever a block in the linked list has been completed. I tried using the XMC_DMA_CH_EnableEvent() and XMC_DMA_CH_SetEventHandler() functions, but I still do not get into my ISR.
Thanks
Rickard
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May 10, 2017
05:12 AM
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May 10, 2017
05:12 AM
Hello, please answer my question. I'm still working on this and need your help.
Best regards
Rickard
Best regards
Rickard
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Aug 08, 2017
04:14 AM
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Aug 08, 2017
04:14 AM
Hi,
Still waiting for an answer.
Thanks.
Still waiting for an answer.
Thanks.
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Aug 09, 2017
10:53 AM
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Aug 09, 2017
10:53 AM
Hi...i am a new user here. My question regards internal flash sector configuration. In previous versions of jlink software this processor had 10 sectors, 0-7 with the length 16kb, 8-128kb, 9-256kb.
Sectors 0-7 are logical sectors. In my application first logical sector is used for code and rest for storing some application data.
This was advantageous since during software download data sectors were not erased. Now, in last 2-3 recent versions of jlink software.
I noticed that sectors become only 4, 0-64kb, 1-64kb, 2-128kb, 3-256kb. Such organization is causing that application data sectors are erased every time new software is downloaded.
Why of this change? Do you recommend creating my own jflash configuration file with previous settings?
Once I create this file, how can I make it use by debugger (isystem-winidea) which is using Jlink as debugging interface.
smt assembly
Sectors 0-7 are logical sectors. In my application first logical sector is used for code and rest for storing some application data.
This was advantageous since during software download data sectors were not erased. Now, in last 2-3 recent versions of jlink software.
I noticed that sectors become only 4, 0-64kb, 1-64kb, 2-128kb, 3-256kb. Such organization is causing that application data sectors are erased every time new software is downloaded.
Why of this change? Do you recommend creating my own jflash configuration file with previous settings?
Once I create this file, how can I make it use by debugger (isystem-winidea) which is using Jlink as debugging interface.
smt assembly
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Sep 06, 2017
01:24 AM
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Sep 06, 2017
01:24 AM
Hi,
Any update on my issue?
Rickard
Any update on my issue?
Rickard
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Oct 09, 2017
12:49 AM
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Oct 09, 2017
12:49 AM
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Oct 10, 2017
05:05 AM
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Oct 10, 2017
05:05 AM
jferreira wrote:
Hi,
See attached modified main.c file to enable 16bit duty cycles and enabling interrupt that signals that a block transfer is finished.
Regards,
Jesus
Thanks Jesus, it works just like I wanted.
Rickard