Not applicable
Jan 23, 2017
11:49 PM
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Jan 23, 2017
11:49 PM
Hi,
after transmitting many Bytes (more than the rx fifo can hold) to an spi eeprom I would like to flush the receive fifo by setting TRBSCR->FLUSHRB to 1. But the receive fifo will not be cleared. A second write to TRBSCR->FLUSHRB with 1 clears it. That behaviour occurs when the rx fifo is full.
If the rx fifo is not full (but holds some elements) I need to write TRBSCR->FLUSHRB only once (as noted in the datasheet).
USIC1 CH0 and CH1 are configured for 16 rx and 16 tx fifo Slots each. (64 fifo Slots on XMC4500 availabe).
Why do I Need to flush the rx fifo twice?
Regards
Tobias
after transmitting many Bytes (more than the rx fifo can hold) to an spi eeprom I would like to flush the receive fifo by setting TRBSCR->FLUSHRB to 1. But the receive fifo will not be cleared. A second write to TRBSCR->FLUSHRB with 1 clears it. That behaviour occurs when the rx fifo is full.
If the rx fifo is not full (but holds some elements) I need to write TRBSCR->FLUSHRB only once (as noted in the datasheet).
USIC1 CH0 and CH1 are configured for 16 rx and 16 tx fifo Slots each. (64 fifo Slots on XMC4500 availabe).
Why do I Need to flush the rx fifo twice?
Regards
Tobias
2 Replies
Not applicable
Jan 25, 2017
04:18 AM
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Jan 25, 2017
04:18 AM
Ok, got it. The FIFO is cleared after flush. But after flush both RBUF Registers will be copied into the FIFO. So you Need to flush twice.
Jan 26, 2017
05:17 AM
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Jan 26, 2017
05:17 AM
Or you can call "XMC_SPI_CH_GetReceivedData" twice to clear RBUF0 and RBUF1 before flushing RXFIFO. However, I believe flushing RXFIFO twice is faster then this approach.
Best regards,
Deni
Best regards,
Deni