How to know the state(ideal/Busy) of other cores(core1/2) from the master core(core0)

[User11926]

Hello,

I want to know the status of the other cores i.e, core 1 and core 2 CPU's are in ideal state or busy state from the core 0.

Is there any possible way to know the status of other cores.

Thank You.


Regards,

Venkat

[#2]

What do you mean by busy ? Can you please elaborate ?

[User9888]

Venkat wrote:
Hello,

I want to know the status of the other cores i.e, core 1 and core 2 CPU's are in ideal state or busy state from the core 0.

Is there any possible way to know the status of other cores.

Thank You.


Regards,

Venkat

Hi Venkat,

The status of the other cores can be obtained via the debug status register (DBGSR). The workings of this register is explained in the IFX Core Architecture User Manual.

Best regards,

Henk-Piet Glas
Technical Product Specialist

[rogeliokamryn]

1. Multicore Communication Setup:

   • Implement a shared data structure or variables accessible by all cores, such as a status flag or a register.
   • Ensure that the master core (Core0) writes the current state (idle/busy) to this shared data structure.

2. Inter-Core Signaling Mechanism:

   • Utilize inter-processor communication techniques like mailbox or message passing to signal the state between cores.
   • Define specific messages or flags that indicate the ideal or busy state of the other cores.

3. Polling Mechanism:

   • Implement a periodic polling mechanism on Core0 to check the shared data structure for updates on the state of other cores.
   • Adjust the polling frequency based on the desired responsiveness and efficiency of the system.

4. Interrupts and Events:

   • Configure interrupts or events triggered by state changes in other cores.
   • Enable Core0 to respond promptly to state changes without continuous polling, optimizing system resource utilization.

5. Synchronization Primitives:

   • Use synchronization primitives like semaphores or mutexes to ensure safe access to shared data and prevent data inconsistency issues.

6. Cricket Updates Integration:

   • Embed the logic for retrieving and processing cricket updates within the master core (Core0).
   • Leverage the established communication mechanisms to coordinate the processing of cricket updates on other cores as needed.

7. Example Implementation:

   • When Core1 or Core2 is actively processing cricket updates, set the corresponding state flag to 'Busy.' Conversely, set the state to 'Idle' during periods of inactivity.
   • Ensure that the cricket updates are seamlessly integrated with the multicore communication framework, allowing the master core to monitor and respond to the state changes effectively.