Jun 24, 2016
08:06 AM
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Jun 24, 2016
08:06 AM
Hello,
is it possible to get the number of received clocks? I have a Spi with DMA transfer and it is necessary for me to detect the number of clocks.
If I receive an additional clock pulse my data transfer isn't valid any more.
Are there any solutions for the XMC4800?
Thank you very much.
is it possible to get the number of received clocks? I have a Spi with DMA transfer and it is necessary for me to detect the number of clocks.
If I receive an additional clock pulse my data transfer isn't valid any more.
Are there any solutions for the XMC4800?
Thank you very much.
- Tags:
- IFX
1 Reply
Jun 26, 2016
11:27 PM
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Jun 26, 2016
11:27 PM
Hello,
Is the additional clock pulse due to noise or the SPI master may simply transmit more than the defined word size?
The USIC in SPI mode will latch in data with each additional clock pulse.
For example, assume:
- SPI communication is defined for word size = frame size = 8 bits
- SPI master transmits a 9-bit frame instead.
What happens is the following:
- USIC SPI slave latches in the first 8-bits and loads them to the receive buffer location (RBUF0/1 or RxFIFO)
- It latches in the 9th bit as the MSB of a 2nd word.
- And now if it detects the deassertion of the slave select signal (Master deasserts at the end of the 9-bit frame), it loads whatever it has received into the next buffer location.
To answer your question, no, the USIC does not count the number of clocks or bits received.
This can be inferred only through the number of frames received (with RxFIFO, this is with RBFLVL for example).
With DMA transfer, I think the application software has to implement some data integrity checks of the data transferred.
I don't see how the error of additional bit received and the subsequent DMA transfer can be stopped without SW intervention.
Regards,
Min Wei
Is the additional clock pulse due to noise or the SPI master may simply transmit more than the defined word size?
The USIC in SPI mode will latch in data with each additional clock pulse.
For example, assume:
- SPI communication is defined for word size = frame size = 8 bits
- SPI master transmits a 9-bit frame instead.
What happens is the following:
- USIC SPI slave latches in the first 8-bits and loads them to the receive buffer location (RBUF0/1 or RxFIFO)
- It latches in the 9th bit as the MSB of a 2nd word.
- And now if it detects the deassertion of the slave select signal (Master deasserts at the end of the 9-bit frame), it loads whatever it has received into the next buffer location.
To answer your question, no, the USIC does not count the number of clocks or bits received.
This can be inferred only through the number of frames received (with RxFIFO, this is with RBFLVL for example).
With DMA transfer, I think the application software has to implement some data integrity checks of the data transferred.
I don't see how the error of additional bit received and the subsequent DMA transfer can be stopped without SW intervention.
Regards,
Min Wei