SPI clock generation problem

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Hi!

I'm trying to configure the SPI interface using the DAVE app SPI_MASTER. I set up everything and looked at the waveforms in my oscilloscope.

I made several screenshots with different clocks.

This is for 10MHz:
1999.attach

This is for 20MHz:
2000.attach

And this is for 25MHz:
2001.attach

So what is happening at 25MHz? Why is the clock looking so ugly? At 20MHz it seems fine. Does anyone have an idea?

Thanks!

Regards,
Milad
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chismo
Employee
Employee
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Hello Milad,

Which device are you using?
I suspect that this could be due to the 1 module clock jitter introduced by the fractional divider.
The faster the baud rate, the more significance of this jitter.

Regards,
Min Wei
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Hello Min Wei,

I'm using the XMC4500 Relax Kit for now.

Is there any solution to this problem? Or does this problem always occur with higher frequencies?

Regards,
Milad
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chismo
Employee
Employee
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Hello Milad,

Yes, the jitter is more significant with higher frequencies.

Is 25 Mbps a hard requirement for your application?
XMC4500 is running at 120 MHz system clock. And we can't divide this clock down to 25 MHz with a whole number.

One alternative could be to adjust the PLL such that the system clock is changed to a multiple of 25 MHz, e.g. 100 MHz.
This way, we can avoid using the fractional divider.

Regards,
Min Wei
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Hello Min Wei,

25MHz is not a hard requirement. But it would be nice if it was above 20MHz.
With 120MHz it should be possible then to use a SPI clock frequency of 24MHz or even 30MHz as this is a whole number. But the jitter also happens there...I can't seem to use a frequency above 20MHz without jitter.

Regards,
Milad
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chismo
Employee
Employee
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Hello Milad,

I have tried to generate a 30 MHz clock using the normal divider mode of the baud rate generator (BRG) by adding the lines:

/* Selecting normal divider mode, STEP = 1023*/
SPI_MASTER_0.channel->FDR = 0x43FF;
/* Changing PDIV from 0 to 1 */
SPI_MASTER_0.channel->BRG |= 0x10000;

With the above settings, the baud rate is simply 120 MHz divided by 4.

I do see also some jittering on the clock.
I will check further to understand the expected behaviour here.

Regards,
Min Wei
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Hello Min Wei,

I experience the jittering already at frequencies above 10MHz. At least this is the hard limit for my circuit where communication ceases to operate. It is not dependant on the circuit because with another microcontroller I can reach a frequency of 22,5MHz.

Regards,
Milad
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chismo
Employee
Employee
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Hello Milad,

With my previous experiment with 30 MHz SPI clock, I see that the clock cycle periods varies from about 32 ns to 35 ns.
I understand now that this jitter is due to PLL output and is expected.

Separately, the SPI is a synchronous protocol and should be more tolerant to jitter.
Do you see actual SPI failure or your application has a specific jitter requirement?

Note that in our data sheets, the max. accumulated jitter at fsys is +/- 5ns over 300 clock cycles.

Regards,
Min Wei
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