SDRAM over EBU

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Hello,

I am trying to get the SDRAM runnig over the EBU interface.
But when i'm testing the device i'm loosing most of the data.
I am using DAVE v4.1.4 with the XMC library.

Is there any example code how to use the SDRAM interface properly?

Here is my full configuration:


XMC_EBU_CONFIG_t EBU_Config =
{
.ebu_clk_config.ebu_clock_divide_ratio = XMC_EBU_CLOCK_DIVIDED_BY_1, //Vorher XMC_EBU_CLOCK_DIVIDED_BY_2
.ebu_clk_config.ebu_div2_clk_mode = XMC_EBU_DIV2_CLK_MODE_OFF, //XMC_EBU_DIV2_CLK_MODE_ON
.ebu_clk_config.ebu_clk_mode = XMC_EBU_CLK_MODE_SYNCHRONOUS_TO_CPU, //Vorher XMC_EBU_CLK_MODE_SYNCHRONOUS_TO_CPU
.ebu_mode_config.ebu_sdram_tristate = false, .ebu_mode_config.ebu_extlock = false, .ebu_mode_config.ebu_arbsync = true, .ebu_mode_config.ebu_arbitration_mode =
XMC_EBU_ARB_MODE_SOLE_MASTER_MODE, .ebu_mode_config.bus_timeout_control = 0xFFU, .ebu_mode_config.ebu_ale_mode = XMC_EBU_ALE_OUTPUT_IS_INV_ADV,
.ebu_free_pins_to_gpio.address_pins_gpio = 0x1ff, .ebu_free_pins_to_gpio.adv_pin_gpio =
false };


XMC_EBU_REGION_t EBU_Config_Region=
{ .read_config =
{
.ebu_region_no = EBU_SDRAM, //
.ebu_bus_read_config =
{ .ebu_burst_length_sync = XMC_EBU_BURST_LENGTH_SYNC_1_DATA_ACCESS, //[FETBLEN]
.ebu_burst_buffer_sync_mode = XMC_EBU_BURST_BUFFER_SYNC_LENGTH_SYNC_ENABLE, //
.ebu_read_stages_synch = XMC_EBU_READ_STAGES_SYNC_ONE, //Only one Sync-Stage
.ebu_burst_flash_clock_feedback = XMC_EBU_BURST_FLASH_CLOCK_FEEDBACK_DISABLE, //
.ebu_burst_flash_clock_mode = XMC_EBU_BURST_FLASH_CLOCK_MODE_RUN_CONTINUOSLY, //
.ebu_early_chip_select_sync_burst = XMC_EBU_EARLY_CHIP_SELECT_DELAYED, //nCS Delayed
.ebu_burst_signal_sync = XMC_EBU_BURST_SIGNAL_SYNC_BURST_ADV_DELAYED, //nADV Delayed
.ebu_burst_address_wrapping = XMC_EBU_BURST_ADDRESS_WRAPPING_DISABLED, //
.ebu_wait_signal_polarity = XMC_EBU_WAIT_SIGNAL_POLARITY_PIN_ACTIVE_LOW, //Polarity of nWait
.ebu_byte_control = XMC_EBU_BYTE_CONTROL_FOLLOWS_CONTROL_SIGNAL_TIMMING, //[BCGEN]
.ebu_device_addressing_mode = XMC_EBU_DEVICE_ADDRESSING_MODE_16_BITS, //[PORTW]
.ebu_wait_control = XMC_EBU_WAIT_CONTROL_OFF, //
.ebu_asynchronous_address_phase = false, //
.ebu_device_type = XMC_EBU_DEVICE_TYPE_SDRAM, //[AGEN]
.ebu_recovery_cycles_between_different_regions = 0xfU, //[RDDTACS]
.ebu_recovery_cycles_after_read_accesses = 0x7U, //[WRRECOVC]
.ebu_programmed_wait_states_for_read_accesses = 0x9U, //[WAITWRC]
.ebu_freq_ext_clk_pin = 1, //[EXTCLOCK]
.ebu_ext_data = 0, //[EXTDATA]
.command_delay_lines = 0xfU, //[CMDDELAY]
.address_hold_cycles = 0xfU, //[AHOLDC]
.address_cycles = 0xfU //[ADDRC]
}
} //
,
.write_config =
{
.ebu_region_no = EBU_SDRAM, .ebu_bus_write_config =
{ .ebu_burst_length_sync = XMC_EBU_BURST_LENGTH_SYNC_1_DATA_ACCESS, //[FETBLEN]
.ebu_burst_buffer_sync_mode = XMC_EBU_BURST_BUFFER_SYNC_LENGTH_SYNC_ENABLE, //
.ebu_early_chip_select_sync_burst = XMC_EBU_EARLY_CHIP_SELECT_DELAYED, //nCS Delayed
.ebu_burst_signal_sync = XMC_EBU_BURST_SIGNAL_SYNC_BURST_ADV_DELAYED, //nADV Delayed
.ebu_wait_signal_polarity = XMC_EBU_WAIT_SIGNAL_POLARITY_PIN_ACTIVE_LOW, //Polarity of nWait
.ebu_byte_control = XMC_EBU_BYTE_CONTROL_FOLLOWS_CONTROL_SIGNAL_TIMMING, //[BCGEN]
//.ebu_device_addressing_mode = XMC_EBU_DEVICE_ADDRESSING_MODE_16_BITS, //[PORTW]
.ebu_wait_control = XMC_EBU_WAIT_CONTROL_OFF, //
.ebu_asynchronous_address_phase = false, //
.ebu_lock_chip_select = false, //
.ebu_device_type = XMC_EBU_DEVICE_TYPE_SDRAM, //[AGEN]
.ebu_recovery_cycles_between_different_regions = 0xfU, //[RDDTACS]
.ebu_recovery_cycles_after_write_accesses = 0x7U, //[RDRECOVC]
.ebu_programmed_wait_states_for_write_accesses = 0x9U, //[WAITRDC]
.ebu_freq_ext_clk_pin = 1, //[EXTCLOCK]
.ebu_ext_data = 0, //[EXTDATA]
.command_delay_lines = 0xfU, //[CMDDELAY]
.address_hold_cycles = 0xfU, //[AHOLDC]
.address_cycles = 0xfU //[ADDRC]
}
} //
}

XMC_EBU_SDRAM_CONFIG_t EBU_Config_SDRAM =
{ //SDRMCON
.ebu_sdram_clk_mode = XMC_EBU_SDRAM_CLK_MODE_CONTINUOUSLY_RUNS, /**< SDRAM clock mode select [SDCMSEL]*/
.ebu_sdram_pwr_mode = 0,/**< Power Save Mode used for gated clock mode [PWR_MODE]*/
.ebu_sdram_clk_output = 0,/***< Disable SDRAM clock output [CLKDIS]*/
.ebu_sdram_row_cycle_time_counter_extension = 0x01UL, /** .ebu_sdram_mask_for_bank_tag = XMC_EBU_SDRAM_MASK_FOR_BANK_TAG_ADDRESS_23_to_22, /**< Mask for Bank Tag [BANKM]*/
.ebu_sdram_mask_for_row_tag = XMC_EBU_SDRAM_MASK_FOR_ROW_TAG_ADDRESS_26_to_10, /**< Mask for Row Tag [ROWM]*/
.ebu_sdram_row_cycle_time_counter = 0x00UL,/**< Row cycle time counter: Insert (CRCE * 😎 + CRC + 1 NOP cycles [CRC]*/
.ebu_sdram_row_to_column_delay_counter = 0x03U,/**< (CRCD) Number of NOP cycles between a row address and a column address: Insert CRCD + 1 NOP cycles [CRCD]*/
.ebu_sdram_width_of_column_address = XMC_EBU_SDRAM_WIDTH_OF_COLUMN_ADDRESS_8_to_0,/**< Number of address bits from bit 0 to be used for column address [AWIDTH]*/
.ebu_row_precharge_time_counter = 0x3U,/**< (CRP) Number of NOP cycles inserted after a precharge command: Insert CRP + 1 NOP cycles [CRP]*/
.ebu_mode_register_set_up_time = 0x01U,/**< (CRSC) Number of NOP cycles after a mode register set command: Insert CRSC + 1 NOP cycles [CRSC]*/
.ebu_init_refresh_commands_counter = 0x04U, /**< (CRFSH) Number of refresh commands issued during powerup init sequence: Perform CRFSH + 1 refresh cycles [CRFSH]*/
.ebu_row_precharge_delay_counter = 0x02U, /**< Number of clock cycles between row activate command and a precharge command [CRAS]*/

//SDRMOD
.ebu_sdram_burst_length = XMC_EBU_SDRAM_BURST_LENGTH_4_LOCATION, //[BURSTL]
.ebu_sdram_casclk_mode = XMC_EBU_SDRAM_CAS_LATENCY_2_CLKS, //[CASLAT]
.ebu_sdram_cold_start = 0x1U, //[COLDSTART]
.ebu_sdram_extended_operation_mode = 0, //[XOPM]
.ebu_sdram_extended_operation_bank_select = 0, //[XBA]

//SDRMREF
.ebu_sdram_num_refresh_counter_period = 28, //[REFRESHC]
.ebu_sdram_num_refresh_cmnds = 2, //[REFRESHR]
.ebu_sdram_self_refresh_exit = true, //[SELFREX]
.ebu_sdram_self_refresh_entry = 0, //[SELFREN]
.ebu_sdram_auto_self_refresh = 0, //[AUTOSELFR]
.ebu_sdram_extended_refresh_counter_period = 0, //[ERFSHC]
.ebu_sdram_self_refresh_exit_delay = 0xFFU, //[SELFREX_DLY]
.ebu_sdram_auto_refresh = 0x01U, //[ARFSH]
.ebu_sdram_delay_on_power_down_exit = 0x07U //[RES_DLY]
};

Thanks in advance for your help

Cheers

Sven
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Hi Sven,

You can download the full XMCLIb + examples: http://dave.infineon.com/Libraries/XMCLib/XMC_Peripheral_Library_v2.1.4.zip
In the package, it includes examples for all peripheral drivers

I have extracted the example and readme.txt for EBU here.

Regards,
Daryl
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