XMC4500 speed up ISR of sync AD conversion

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Hey guys,

I need your help... again. :S


My Situation:
I'm using DAVE 4 (newest Updates installed) to programm XMC4500 Relax Kit. I configured the ADCs to convert 4 Pins synchronously with queue request. When VADC_G0 result is available an Interrupt occures and I only want to read out my 4 results.
I want to convert at least 100,000 times. So In my ADC ISR I also have to increment a counter. In my main function I'm using a WHILE-Loop to control my counter. If it reaches >=100,000 the ADC will be turned off. A attached an example project here
So far everything is working... as long as I use small sample rates.


My Problem:
If I increase the sample rate the ADC ISR is never leaved.
I tested it in debug mode with DAVE. Although the counter reached the STOP-value the ADC doesn't stop running and keeps incrementing the counter. It never leaves the while-loop and it seems to get stucked in the ISR. Looks like an Interrupt occures faster, then I can read out my results. But is this even possible???? I mean the XMC4500 has120 MHz. Shouldn't that be enough to read out 4 simple ADC results in an ISR????


My approaches:
1. optimization level in compiler
I increased the optimization of my project in the compiler properties to "optimize most -O3". I had a look at the Dissassembly. The assembly code has the same instructions as it had without any optimization. They only changed in order. It seems to use pipeling more now. But the results remain the same.

2. Minimize the ISR
I tried to delete everything in the ISR (except the counter increment). And it worked ! ! I can sample with maximum rate BUT it's useless since I don't read out my results. Only thing I can say now is that obviously my ISR is to long. But I have no idea on how to shorten it or make it more effcient.


Hope you uderstand my problem. Otherwise ask me for more details.

I will be very thankful for any replies and/or hints.



Greetings ,

bqpd
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Travis
Employee
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First solution authored Welcome! 500 replies posted
Hi,

I had tested your software and is able to experience the same behavior which you mentioned above. I believe the CPU is always given the priority to process the ISR such that it ignores the main loop as there is no chance to stop the VADC.

Hence I would prefer you to check the CountMax in the ISR and to stop the VADC conversion in the ISR. Attached is the my project for your reference.



void VADC_Result_ISR(void)
{
uint32_t i;


CountMax++;

// Normal 8channel VADC result register read
for (i=0; i {
// If "wait for read mode" is enabled, do a read of result register is necessary for every interrupt occurrence.
// Otherwise interrupt will happened only once, alternatively you can disable the wait for read mode.
VADC0_G0_result = XMC_VADC_GROUP_GetResult(VADC_G0,i);
VADC0_G1_result = XMC_VADC_GROUP_GetResult(VADC_G1,i);
VADC0_G2_result = XMC_VADC_GROUP_GetResult(VADC_G2,i);
VADC0_G3_result = XMC_VADC_GROUP_GetResult(VADC_G3,i);
}

/* Clear result event */
for (i=0; i {
XMC_VADC_GROUP_ClearResultEvent(VADC_G0,i);
XMC_VADC_GROUP_ClearResultEvent(VADC_G1,i);
XMC_VADC_GROUP_ClearResultEvent(VADC_G2,i);
XMC_VADC_GROUP_ClearResultEvent(VADC_G3,i);
}


#if VADC_HARDWARE_TRIGGER

#else

if(CountMax < MAX)
{
//Software trigger
XMC_VADC_GROUP_QueueTriggerConversion(VADC_G0);
}


#endif

}

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Hallo Travis,

thank you very much for your reply.

My code so far was only for testing proposes. Since I don't want the ADC to stop in my actual project I don't realy need your code example. Nevertheless, thank you for the work around.
I just wanted to know if the CPU can handle the ADC results with highest sample rate and sync conversion. You just confirmed my assumption, that it could not.


I need this high sample rate in my real project for an extern control. A lower rate just causes additional latency. Do you think there is another way to escape from this problem than reducing the sample rate till the cpu can handle the ADC results?
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User10215
Level 4
Level 4
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Hi bqpd,

you might be interested in using the DMA to transfer the results from the ADC-conversion to memory. The DMA copies the data from the result registers of the ADC to a place in RAM with nearly any impact on the CPU.
I found a pretty understandable explenation for the DMA on the infineon website:

http://www.infineon.com/cms/de/product/microcontroller/32-bit-industrial-microcontroller-based-on-ar...

It's the document "AP32290 - XMC4000 - General Purpose Direct Memory Access(GPDMA)". This application note even has an example for transferring ADC-results to RAM using XMCLib.
Perhaps you'll find this useful.

Regards,
Niclas
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Hi Niclas,

I allready had a look at the DMA. I also used this this document to configure it, but I faild several times and stopped working on it.

Since my time for this project is limited and I need to get ready soon I will first try to slow down the ADC. If I have some time remaining at the end I will give another try to the DMA for performance improvment.


But thanks so far for the tips. I will keep them in mind.

Bets Regards,
bpqd
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