Not applicable
Nov 10, 2015
03:59 AM
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Nov 10, 2015
03:59 AM
4 Replies
Not applicable
Nov 12, 2015
01:35 AM
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Nov 12, 2015
01:35 AM
Depends on what kind of interrupt service you are evoking.
Not applicable
Nov 12, 2015
10:43 PM
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Nov 12, 2015
10:43 PM
Pulled down? This the clock.
Nov 12, 2015
11:56 PM
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Nov 12, 2015
11:56 PM
Hello,
Generally, I would say no, the USIC interrupt does not hold SCL low.
One scenario where it may appear so is during a slave read request:
- Master sends the start condition, slave address and read request.
- Addressed slave detects the read request and triggers the SRR interrupt.
- In the SRR service routine, the data for transmission to master is written to TBUF.
- The slave holds SCL low while waiting for the data to be written to TBUF, and not because of any interrupts.
Maybe you can provide more details to the scenario that you encountered?
Regards,
MIn Wei
Generally, I would say no, the USIC interrupt does not hold SCL low.
One scenario where it may appear so is during a slave read request:
- Master sends the start condition, slave address and read request.
- Addressed slave detects the read request and triggers the SRR interrupt.
- In the SRR service routine, the data for transmission to master is written to TBUF.
- The slave holds SCL low while waiting for the data to be written to TBUF, and not because of any interrupts.
Maybe you can provide more details to the scenario that you encountered?
Regards,
MIn Wei
Not applicable
Nov 13, 2015
12:29 AM
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Nov 13, 2015
12:29 AM
1. In your scenario holding SCL low is made by IIC protocol handler or by the user program?
2. Another question: IIC master receive scenario:
For slave transmit on slave I have the following data loop. But I don't know how to add a wait loop for master ACK because the documentation says PSR.ACK set only on master
2. Another question: IIC master receive scenario:
For slave transmit on slave I have the following data loop. But I don't know how to add a wait loop for master ACK because the documentation says PSR.ACK set only on master
while (!(USIC0_CH1->PSR & USIC_CH_PSR_SCR_Msk)) ;
USIC0_CH1->PSCR |= USIC_CH_PSR_SCR_Msk;
for (i=0; iwhile (USIC0_CH1->TCSR & USIC_CH_TCSR_TDV_Msk) ;
USIC0_CH1->PSCR |= USIC_CH_PSR_TBIF_Msk;
flags = XMC_I2C_CH_TDF_SLAVE_SEND << 8U;
USIC0_CH1->TBUF[0] = data | flags;
}