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Thread: XMC4100 Clock Configuration problem

  1. #1
    harshan
    Guest

    XMC4100 Clock Configuration problem

    Hi,
    I am working on XMC4100, my external crystal is 12MHZ, i am configuring the board with pll in normal mode, the below procedure i am following

    fPLL = ( N / (P * K2)) * Fosc

    where Fosc = 12Mhz
    i am taken PDIV = 3 and K2DIV = 4
    i am trying with different N Values and loading into PLLCON0 Register and the result is as below

    N = 80MHZ -----------> configured Successfully
    N = 72MHZ -----------> Configured Successfully
    N = 64MHZ -----------> Configured Successfully
    N = 48MHZ -----------> Configured Successfully
    N = 32MHZ -----------> NOT Configured Successfully
    N = 24MHZ -----------> Configured Successfully
    N = 16MHZ -----------> Configured Successfully
    N = 12MHZ -----------> NOT Configured Successfully
    N = 8MHZ -----------> NOT Configured Successfully
    N = 6MHZ -----------> NOT Configured Successfully
    N = 4MHZ -----------> NOT Configured Successfully
    N = 2MHZ -----------> NOT Configured Successfully
    N = 1MHZ -----------> NOT Configured Successfully

    my doubt is why i am not configured successfully with 32,12,8,6,4,2,1 MHZs

    Note:
    by using Systick with 1ms triggering the event on gpio i am confirming either the clock was set or not.

    Thanks and Regards,
    Harshan

  2. #2
    chismo is on a distinguished road
    Join Date
    Apr 2013
    Posts
    267
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    2451.25
    Hello Harshan,

    If you refer to the data sheet section 3.3.4 on PLL characteristics, the limits of the VCO frequency are 260 MHz to 520 MHz.
    VCO frequency is the frequency before the K2 divider.
    Therefore from your list, only 80 and 72 MHz meets these limits.

    Even though the PLL still managed to lock with some of the frequencies outside of the specified limits, we can't guarantee such frequencies work all the time.
    To achieve a lower PLL frequency, my suggestion is to increase K2 divider value instead.
    For example, to achieve PLL frequency = 8 MHz, use N = 80, PDIV = 3 and K2 = 40.

    Regards,
    Min Wei

  3. #3
    harshan
    Guest
    Thanks for Reply

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