EBU Trouble XMC4500, Clock and Burst Flash

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Dear Engineers,

I ran into several problems using EBU and EBU-Burst Flash Mode, including clock duty cycle, deviation from datasheet register description, uncomplete data transfers ( dropping of EBU transmission) ...
I hope you can help to bring light into these matters and more important how to make it work ( and hopefully point out mistakes I made ).
How to trust EBU that all data will be received and code works in future too. (My project shall be used later by different people without detailed knowledge of XMC/FPGA)

I use EBU for Datatransfer to and from FPGA. Burst Modus if possible to save time. Hardware Control in FPGA, Control Loop in XMC.

XMC => EBU.Region0 -> SDRAM; on Hexagon Board
EBU.Region1 -> FPGA(Burst Flash); not yet connected; logic analyes via Pin Header Board


I have here a XMC4500 Hexagon Board with
XMC4500E144X1024 AC
I use an HDO6054-MS Oscilloscope with 200MS/s logic analyser module.

First Problem: SDCLKO and BFCLKO Timing
I use the code from XMC_Peripheral_Library_v2.0.0 -> XMCLIB -> XMC4500 -> EBU example.
I copy it into a new Dave Project for XMC4500E144X1024

SDCLKO period time is 34ns.
SDCLKO low time is 4.8ns.


	
.ebu_clk_config.ebu_clock_divide_ratio = XMC_EBU_CLOCK_DIVIDED_BY_2,
.ebu_clk_config.ebu_div2_clk_mode = XMC_EBU_DIV2_CLK_MODE_ON,
.ebu_clk_config.ebu_clk_mode = XMC_EBU_CLK_MODE_SYNCHRONOUS_TO_CPU,


As EBU run at half clock speed of CPU (and again via pulse swallowing by 2) I expect a larger SDCLKO low time.
I could work around by operating. But does not feel right to me. Is this a BUG? I found nothing in the Errata Sheet.
	
.ebu_clk_config.ebu_clock_divide_ratio = XMC_EBU_CLOCK_DIVIDED_BY_1,
.ebu_clk_config.ebu_div2_clk_mode = XMC_EBU_DIV2_CLK_MODE_ON,
.ebu_clk_config.ebu_clk_mode = XMC_EBU_CLK_MODE_SYNCHRONOUS_TO_CPU,

.read_config.ebu_bus_read_config.ebu_freq_ext_clk_pin = 0x1U,


I'll add my other problems in following posts.

best regards
Felix
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Biggest problem does not exist. Nothing dropped in Burst Flash Mode

typedef struct {
uint16_t Var1;
uint16_t Var2;
uint16_t Var3;
uint16_t Var4;
uint64_t Var5;
uint64_t Var6;
uint64_t Var7;
uint64_t Var8;
} Fpga_t;

volatile Fpga_t * const pFpga = (volatile Fpga_t * const) ( FPGA_BASE +( 0xA0<<1));

*pFpga = Buf;


Assembler:
08000a08:   ldmia r4!, {r0, r1, r2, r3}
08000a0a: stmia r5!, {r0, r1, r2, r3}
08000a0c: ldmia r4!, {r0, r1, r2, r3}
08000a0e: stmia r5!, {r0, r1, r2, r3}


How it should be (no manual stepping):
1527.attach

What it looks like in normal step mode:
1529.attach

Where you find the rest of the paket:
1528.attach
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