how to configure SPI pins

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Hi,

Not clear how to configure SPI pins in master and slave mode.
Device: XMC1100_T038F0064

In DAVE3 I have made two project with an SPI slave in non RTOS and SPI master in non RTOS mode.
I have debugged this projects. I have found the followings for the pin configirations.


Using Port I/O Functions and USIC Module 0 Channel 1 Interconnects

Master config
--------------
addr = DX0CR, ch: 1, value = 0x00000016
addr = DX3CR, ch: 1, value = 0x00000005
addr = DX5CR, ch: 1, value = 0x00000005

DX0: G, INSW=1 -> DX3INS
DX3: F -> DX5INS
DX5: F -> P1.5 (DIN)

GPIO config: P1.2 : output : ALT7: CH1.DOUT
GPIO config: P1.3 : output : ALT6: CH1.SCLKOUT
GPIO config: P1.4 : output : ALT7: CH1.SELO1


Slave config
------------
addr = DX0CR, ch: 1, value = 0x00000010
addr = DX1CR, ch: 1, value = 0x00000016
addr = DX2CR, ch: 1, value = 0x00000116
addr = DX5CR, ch: 1, value = 0x00000004

DX0: A, INSW=1 P1.3 (DIN)
DX1: G, INSW=1 DX4INS
DX2: G, INSW=1, DPOL=1 DX5INS

GPIO config: P1.2 : output : ALT7 CH1.DOUT0


In master mode for example: I have found only P1.5 configured directly (DIN). DOUT, SCLKOUT and SELO1 configured by GPIO settings. No need to configure the output pins?

In slave mode: shift clock input not configured. What are DXnINS? Some DXnCR configured for DXnINS.
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chismo
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Hello,

Yes, the selection of the output functions are done at the ports via GPIO settings. This is because usually there are also other peripherals' output functions available on the same GPIO. The ports determine which should be the active output function.

Within the peripheral, it is only necessary to configure the behaviour of the output signal. For example, the polarity of the signal can be changed with the bit field SCTR.DOCFG.
Therefore, the SPI master pin configuration looks fine.

For the SPI slave, is the register DX4CR not configured? And what is the intended pin for shift clock input?

DXnINS is the direct output signal from the input stage.
Using the DX2 settings as an example, here I see DX5INS is selected and DX5CR has the value of 0x4.
This means that the data input from DX5E (P1.4) is selected for the DX5 input stage and its output DX5INS is further routed to the DX2 input stage.
Therefore, P1.4 is effectively selected for the DX2 input stage.

Best Regards,
Min Wei
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This settings came from a DAVE3 "spi slave" DAVE_CE generated code.

Slave settings
------------------
For DX5
DX5: E, INSW=0 P1.4 (DX5INS routed ->DX2G) (as you wrote). In this case INSW must be 0? So routing applicable only if INSW=0?
This will be for SELIN? (shift control input)

When I enter the manual pin assignment in DAVE CE and select clock input I will have an explicitly selected SCLKIN


Master
---------
How the chip identifed that it is the master?
With this settings?
GPIO config: P1.3 : output : ALT6: CH1.SCLKOUT
Or when the code addresses BRG it will be the master?

--
I have found this line in the reference manual. What does it mean? So "0" stay instead a port.
USIC0_CH1.DX1D I 0 Shift clock input

--
Device: XMC1100
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chismo
Employee
Employee
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Hello,

For DX5, the setting for INSW needs to be also 1 to derive the signal directly from the pin.
Yes, in this case, the SELIN is from P1.4 through the use of DX5 and DX2 input stages.

The USIC channel itself is generic. It is how the application code sets up the channel that determines if it is used as a master.
But it is probably okay to say that a master is indicated so through the appropriate configuration of the BRG and GPIO.

In the interconnects table for USIC0_CH1.DX1D, the '0' means that this selection is not connected to a pin and instead, always has the value 0.

Best Regards,
Min Wei
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