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Aug 12, 2015
06:47 AM
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Aug 12, 2015
06:47 AM
Hi @all,
we have the XC2269I running with the internal clock. Configured with Dave.
In Dave there is a warning because of the N-DIVIDER (Range: 16 to 40) which is calculated to 51 automatically. We can't change this number.
We ignore the warning and generate code. The compiler will throw an error because of the check in the SCS.c:
c166 E201: ["..\SCS.c" 420/1] #error "SCS_N out of range, different SCS_P required?"
This error is because of the range check of N-DIV:
// Check N divider
#if (SCS_N < 16) || (SCS_N > 40)
# error "SCS_N out of range, different SCS_P required?"
# endif
We can ignore this error by comment the line. Is there any other way to workaround this? Can anyone tell us if this is a critical error or can we actually live with this?
Cheers, Joe
we have the XC2269I running with the internal clock. Configured with Dave.
In Dave there is a warning because of the N-DIVIDER (Range: 16 to 40) which is calculated to 51 automatically. We can't change this number.
We ignore the warning and generate code. The compiler will throw an error because of the check in the SCS.c:
c166 E201: ["..\SCS.c" 420/1] #error "SCS_N out of range, different SCS_P required?"
This error is because of the range check of N-DIV:
// Check N divider
#if (SCS_N < 16) || (SCS_N > 40)
# error "SCS_N out of range, different SCS_P required?"
# endif
We can ignore this error by comment the line. Is there any other way to workaround this? Can anyone tell us if this is a critical error or can we actually live with this?
Cheers, Joe
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3 Replies
Aug 13, 2015
03:29 AM
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Aug 13, 2015
03:29 AM
Hello Joe,
It seems that this range check is implemented to ensure that with the VCOSEL setting of 0x1, the NDIV does not exceed the range 16 to 40.
From the specification, exceeding these limits might result in unstable operation of the PLL.
To configure for NDIV = 51, the VCOSEL setting (in PLLCON0 register) has to be changed to 0x2.
But from the DAVE tool, I can't find a way to do this.
A manual override of the following line in scs.c is possible though:
to:
Best Regards,
Min Wei
It seems that this range check is implemented to ensure that with the VCOSEL setting of 0x1, the NDIV does not exceed the range 16 to 40.
From the specification, exceeding these limits might result in unstable operation of the PLL.
To configure for NDIV = 51, the VCOSEL setting (in PLLCON0 register) has to be changed to 0x2.
But from the DAVE tool, I can't find a way to do this.
A manual override of the following line in scs.c is possible though:
// Select VCO band 1; VCOSEL = 1
SCU_PLLCON0 |= 4U;
to:
// Select VCO band 2; VCOSEL = 2
SCU_PLLCON0 |= 8U;
Best Regards,
Min Wei
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Aug 14, 2015
03:06 AM
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Aug 14, 2015
03:06 AM
Hello Min Wei,
we tried this workaround and it works just fine. The only disadvantage is that we always have to change the scs.c after code generation with Dave. Maybe we find a way to implement this automatically in a Pre-compile Hookfunction. Does Dave offer any scripting or api-methods?
Thank you for your help.
br, Joe
we tried this workaround and it works just fine. The only disadvantage is that we always have to change the scs.c after code generation with Dave. Maybe we find a way to implement this automatically in a Pre-compile Hookfunction. Does Dave offer any scripting or api-methods?
Thank you for your help.
br, Joe
Aug 16, 2015
08:15 PM
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Aug 16, 2015
08:15 PM
Hello Joe,
I am not aware of such options with the DAvE.
But I have to admit the mentioned workarounds are not very intelligent. Let me check if there are better ways to configure the clock properly.
Regards,
Min Wei
I am not aware of such options with the DAvE.
But I have to admit the mentioned workarounds are not very intelligent. Let me check if there are better ways to configure the clock properly.
Regards,
Min Wei