XC2365B SSC Problem —— time sequence

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I need XC2365B working on slave mode, MSB,
thet data bit (both MISO & MOSI) is transmitted and received in with the rising edge of SCLK.

But it transmitted with the falling edge.
I know it can be configgered in Master mode, but what about Slave mode.
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chismo
Employee
Employee
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Hello,

The USIC SSC slave is by default transmitting on the leading (rising) edge, and receiving on the trailing (falling) edge. The polarity can be changed with DX1CR.DPOL.
MSB first can be selected by SCTRL.SDIR = 1.

Do you really mean that you need the data bit to be transmitted and received with the same edge (rising)? This contradicts the SSC Protocol?

Regards,
Min Wei
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Yes, it's just like this.
I just use XC2365B to simulate a BOSCH Sensor, working on slave mode,
the time sequence like the image.
1440.attach


chismo wrote:
Hello,

The USIC SSC slave is by default transmitting on the leading (rising) edge, and receiving on the trailing (falling) edge. The polarity can be changed with DX1CR.DPOL.
MSB first can be selected by SCTRL.SDIR = 1.

Do you really mean that you need the data bit to be transmitted and received with the same edge (rising)? This contradicts the SSC Protocol?

Regards,
Min Wei
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chismo
Employee
Employee
First like received
Okay, I understand your requirements now, which are:
- slave SSC to output the first data bit with chip select active, before the first clock edge from master SSC.
- and subsequently receive on the leading (rising) edges and transmitting on the trailing (falling) edges.

As a master, the USIC SSC can be easily configured to support such a protocol by delaying the output shift clock by 1/2 cycle.
But as a slave, this is not directly supported.

I would suggest a partial software solution which is to:
- use the idle state defined by SCTRL.PDL control bit to provide the first bit.
- transmit the remaining data through the transmit buffer but shifted by 1.
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Thank you very much.
the idear would be usefully,
thank you again.



chismo wrote:
Okay, I understand your requirements now, which are:
- slave SSC to output the first data bit with chip select active, before the first clock edge from master SSC.
- and subsequently receive on the leading (rising) edges and transmitting on the trailing (falling) edges.

As a master, the USIC SSC can be easily configured to support such a protocol by delaying the output shift clock by 1/2 cycle.
But as a slave, this is not directly affected.

I would suggest a partial software solution which is to:
- use the idle state defined by SCTRL.PDL control bit to provide the first bit.
- transmit the remaining data through the transmit buffer but shifted by 1.
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