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Jun 03, 2015
12:29 AM
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Jun 03, 2015
12:29 AM
Hi!
I currently battle with large propagation delays, due to opto couplers, which means that the data received from slave (MISO) is slightly misaligned in regards to the negative flank of the clock signal (SCLK). Thus I'm looking to delay the shift register clock for incoming data as Figure 17-46 kindly suggests.
However, I fail to see how the shift clock signal is delayed 1/4(?) of a SCLK period (method 2 in Figure). Here's an extract from the same chapter;
This make no sense to me. Could someone break this down and clarify? Shouldn't "SCLK at master (Receive data path)" get delayed 1/2 a SCLK period? How does it know the delay of "SCLK at slave (input drive state)"?
Cheers!
I currently battle with large propagation delays, due to opto couplers, which means that the data received from slave (MISO) is slightly misaligned in regards to the negative flank of the clock signal (SCLK). Thus I'm looking to delay the shift register clock for incoming data as Figure 17-46 kindly suggests.
However, I fail to see how the shift clock signal is delayed 1/4(?) of a SCLK period (method 2 in Figure). Here's an extract from the same chapter;
If the receive shift clock signal in master mode is directly taken from the input function in
parallel to the output signal, the output delay of the master device’s shift clock output is
compensated and only the difference between the input delays of the master and the
slave devices have to be taken into account instead of the complete master’s output
delay and the slave’s input delay of the shift clock path. The delay compensation is
enabled with DX1CR.DCEN = 1 while DX1CR.INSW = 0 (transmit shift clock is taken
from the baud-rate generator).
This make no sense to me. Could someone break this down and clarify? Shouldn't "SCLK at master (Receive data path)" get delayed 1/2 a SCLK period? How does it know the delay of "SCLK at slave (input drive state)"?
Cheers!
5 Replies
Jun 03, 2015
03:28 AM
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Jun 03, 2015
03:28 AM
Hi,
Unfortunately, the mentioned feature is not working. There is an erratum USIC_AI.008 that indicates this.
In any case, the idea with the master mode delay compensation is the following:
- the baud rate generator generates the shift clocks for data transmission and reception.
- for data reception, this is by default the trailing edge of the shift clock. However, there is an expected internal delay to output the shift clock on the SCLKOUT line due to the output stage of the pin.
- with the compensation feature, the output signal from the pin is additionally routed back to the USIC, to be used as the reference for the receive clock edge.
- this way, the output delay of the pin is compensated.
Best Regards,
Min Wei
Unfortunately, the mentioned feature is not working. There is an erratum USIC_AI.008 that indicates this.
In any case, the idea with the master mode delay compensation is the following:
- the baud rate generator generates the shift clocks for data transmission and reception.
- for data reception, this is by default the trailing edge of the shift clock. However, there is an expected internal delay to output the shift clock on the SCLKOUT line due to the output stage of the pin.
- with the compensation feature, the output signal from the pin is additionally routed back to the USIC, to be used as the reference for the receive clock edge.
- this way, the output delay of the pin is compensated.
Best Regards,
Min Wei
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Jun 04, 2015
02:51 AM
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Jun 04, 2015
02:51 AM
chismo wrote:
Hi,
Unfortunately, the mentioned feature is not working. There is an erratum USIC_AI.008 that indicates this.
In any case, the idea with the master mode delay compensation is the following:
- the baud rate generator generates the shift clocks for data transmission and reception.
- for data reception, this is by default the trailing edge of the shift clock. However, there is an expected internal delay to output the shift clock on the SCLKOUT line due to the output stage of the pin.
- with the compensation feature, the output signal from the pin is additionally routed back to the USIC, to be used as the reference for the receive clock edge.
- this way, the output delay of the pin is compensated.
Best Regards,
Min Wei
chismo: Alright, great to know! So the idea with the delay compensation is just to make sure the output clock and input clock are in sync? I.e. nothing to do with propagation delays outside of the XMC?
But does Complete Closed Loop Delay Compensation still work?
Jun 05, 2015
12:33 AM
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Jun 05, 2015
12:33 AM
Yes, that is the idea.
I am afraid the complete closed loop delay compensation is also not working.
I am afraid the complete closed loop delay compensation is also not working.
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Jun 06, 2015
09:49 AM
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Jun 06, 2015
09:49 AM
That was extremely vital information. Thank you!
Any ETA for next revision (D?) where this is fixed?
Any ETA for next revision (D?) where this is fixed?
Dec 29, 2023
07:30 AM
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Dec 29, 2023
07:30 AM
USIC/SPI delay compensation refers to the correction mechanisms implemented to address delays in Ultrasonic Impulse Capture (USIC) and Serial Peripheral Interface (SPI) technologies. These compensations ensure accurate timing and synchronization in data transmission and reception. The complexity of these systems demands precision to mitigate delays and maintain optimal functionality.
Regarding the keyword "ai death calculator," it seems unrelated to USIC/SPI delay compensation. If you have specific questions about AI death calculators or a related topic, please provide more details for accurate assistance.