I2C stop condition interrupt

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User8683
Level 4
Level 4
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Hello,

I have been encountering a condition where the the I2C master and the I2C slave (XMC1100) get out of sync and the master is awaiting more data while the slave thinks it is done.

In trying to fix this, I am trying to understand 2 things but the reference manual is incomplete:

1) HDEL - how to calculate it. It refers to Fppp and Fperiph but Fppp is defined as Fin and Fin is not defined. Fperiph is defined as the module clock. Is that the same as the master clock?

2) How to enable the stop condition interrupt so that I can use it to check that the master has received all data? I have been unable to extract the necessary information by building a DAVE app.
Where are the IRQ numbers for the protocol specific interrupts defined?

I have tried the following:


I2CRegs->PCR_IICMode |= ((((uint32_t)slaveAddress << 1+8) << USIC_CH_PCR_IICMode_SLAD_Pos) & USIC_CH_PCR_IICMode_SLAD_Msk)
| (((uint32_t)SHIFT_ONE << USIC_CH_PCR_IICMode_STIM_Pos) & USIC_CH_PCR_IICMode_STIM_Msk)
| (((uint32_t)SHIFT_ONE << USIC_CH_PCR_IICMode_PCRIEN_Pos) & USIC_CH_PCR_IICMode_PCRIEN_Msk)
| (((uint32_t)SHIFT_ONE << USIC_CH_PCR_IICMode_SRRIEN_Pos) & USIC_CH_PCR_IICMode_SRRIEN_Msk)
| (((uint32_t)SHIFT_ONE << USIC_CH_PCR_IICMode_ERRIEN_Pos) & USIC_CH_PCR_IICMode_ERRIEN_Msk);

NVIC_SetPriority( (IRQn_Type)USIC0_0_IRQn, 3); //IRQ_Hdlr_9 - This works and enables the I2C error exceptin
NVIC_EnableIRQ( USIC0_0_IRQn );
NVIC_SetPriority( (IRQn_Type)USIC0_1_IRQn, 3); //IRQ_Hdlr_10 - This works and enables a read request exception
NVIC_EnableIRQ( USIC0_1_IRQn );
NVIC_SetPriority( (IRQn_Type)USIC0_2_IRQn, 3); //IRQ_Hdlr_11 - This does not work
NVIC_EnableIRQ( USIC0_2_IRQn );
NVIC_SetPriority( (IRQn_Type)26, 3); //IRQ_Hdlr_11 - This does not work
NVIC_EnableIRQ( 26 );



Yet, from the DAVE generated code, the IRQ would appear to be 26 but this does not work if used directly:



const NVIC002_HandleType NVIC002_Handle2 = {
/* Mapped NVIC Node */
.NodeID = 26 ,
/* Node Interrupt Priority */
.Priority = 3,
/* Node Interrupt SubPriority */
.SubPriority = 0,
/* Interrupt enable for Node26 */
.InterruptEnable = 0
};


I would appreciate a code block that shows how to enable the stop condition interrupt. DAVE is not helping get the understanding of these interrupts nor can I use it directly as my code is too large if I use the generated code.
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2 Replies
chismo
Employee
Employee
First like received
Hi longtimer,

For question 1):
- Fpin is by default the fractional divider frequency Ffd unless you are using an external clock source through DX1 input stage. Selection is done through BRG.CLKSEL register bit field.
- Fperiph is the module clock and in XMC1100's case, equivalent to the system main clock MCLK.
- To calculate HDEL, let's use the example setting of MCLK=32MHz, STEP=640, which gives Ffd = 32*640/1024 = 20MHz.
Assume BRG.PPPEN=0 and without digital filter, solving the equation gives HDEL >= 6.125, which means HDEL must be at least 7.

For question 2):
- The IIC stop condition can generate an USIC protocol interrupt, which can be routed to any of the 6 USIC interrupts through the register bit field INPR.PINP.
- For XMC1100, USIC.SR0...SR5 corresponds to NodeID 9...14. For example, INPR.PINP=5 selects NodeID14 (SR5).
- Besides activating and configuring the interrupt node in the NVIC, the interrupt event enable bit PCR_IICMode.PCRIEN has be to set to 1 too.

Regards,
Min Wei
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User8683
Level 4
Level 4
First like received
Hi Min Wei,

Thanks for the details. Can you pass along to get the documentation fixed such that Fin is update to be Fpin as you pointed out. Fin is hard to find in the document so I was not sure if I was missing it somewhere.

It would also be good to have what you stated about the SR 0-5 corresponding to Node 9-14 through INPR.PINP stated explicitly. I was trying to route each interrupt type to its own handler but with only one INPR register, that obviously cannot be done.

Thanks,

Jason
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