RS232 flow control on XMC4500 USIC

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cross mob
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Hi,

I have read the reference manual in order to understand if it's possible to set up the USIC module on a XMC4500 for RS232 with flow control "RTS/CTS (RTR/CTS)". However, I not been able to understand whether it's possible or not so I would really appreciate some hints here. Hopefully somebody has experience from a similar setup or other useful information..?

For instance:
- Can DX1/DX2 stages be used for "CTS"?
- How can I generate a "RTR"?

Best regards,
Johan
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2 Replies
chismo
Employee
Employee
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Hi Johan,

I think this should be possible.

For the traditional RTS/CTS handling, RTS can be realized simply with a general purpose output (GPO) pin and CTS with the DX2 input stage.
For example, the following can be configured:
- DX2CR.DSEL to select the input pin used for CTS
- DX2CR.INSW = 1 to use the input pin as it is
- DX2CR.CM to configure the edge to trigger the transmit data transfer
- TCSR.TDVTR = 1 to start the transfer only when there is a valid edge at DX2
This way, the software can set RTS and write the transmit data to TBUFx or FIFO, and once CTS is received, the data transfer is automatically started.

For RTR/CTS handling, I think the RTR will always be active to indicate data can be received unless the DTE is already receiving a data in the first place. Is this the correct understanding?
For this, we can use a GPO pin as RTR and control its level based on Receiver Start (PSR.RSIF) and Receive Frame Finished (PSR.RFF) events.

Regards,
Min Wei
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Hello!

I have implemented what was suggested by chismo regarding RTS/CTS handling and this approach works well if the CTS input is edge based. But I need to implement RTS/CTS flow control which i level based to communicate with an FTDI chip.

The FTDI chip will keep its RTS pin low for as long as it can accept new data and only set RTS high while unable to accept data. This means that no flanks are sent during normal operation, so my application is never triggered to transmit data.

Is there another way to control the DXnT trigger? In the data sheet I can only find information for edge triggering, configured via DX2CR.CM.
Is it possible to configure the CPU to not clear TCSR.TE after data has been loaded into the shift register? If this bit could be set/reset only on flanks on the CTS pin, it would solve my problem.

BR,
Karl-Johan
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