XMC1300 PWM output problem

[#1]

Hi All,

I have a problem to output the correct PWM signal when set duty cycle as 100%.
In my program, I set the PWM duty cyle as 100%, 100%, 100%, 80%, 50%, 25%, 100%......, the period value is 250us, all the compare values are updated only at the One match event.

From the scope, I can see the PWM signal with duty cycle 80% (after the signal of duty cycle 100%) is not symmetrical,
I assume the correct PWM signal should be the one shown in second picture.

Could someone please give me some suggestions? Thanks a lot.

[#2]

Hi honglinshi,

I believe you are using Center aligned mode.
Did you set the value for both Compare register 1 and compare register 2?

[#3]

Jackson wrote:
Hi honglinshi,

I believe you are using Center aligned mode.
Did you set the value for both Compare register 1 and compare register 2?

Yes, you are correct, the centre aligned mode is used, but only one compare value is used and updated.

The tricky point is only the pulse after the pulse with 100% duty cycle has problem.

[#4]

Hi honglinshi,

On the last 100% duty cycle, can you try set the CR2 to 1?
Only after that you change to other duty cycle.
I guess the behavior is observed because there is no compare value at CR2 when the 100% duty cycle ends.
Hence, no toggling is done before the waveform change to the 80% duty cycle.

[#5]

Jackson wrote:
Hi honglinshi,

On the last 100% duty cycle, can you try set the CR2 to 1?
Only after that you change to other duty cycle.
I guess the behavior is observed because there is no compare value at CR2 when the 100% duty cycle ends.
Hence, no toggling is done before the waveform change to the 80% duty cycle.

Hi Jackson,

Thanks for your reply, I will set CR2 to 1 for the last 100% duty cycle to check the result.

In my test code, the CR2 will be updated at the One match event only, the new compare value at CR2 will be updated before or at the same time of 100% duty cycle ends?

I think your explaination "no toggling is done before the waveform change to the 80% duty cycle" makes sense, but if the new compare value is updated at One match event,
the new duty cycle after the 100% duty cycle will be not correct, is this a bug? is there any solution to solve this problem? In practise, it is not easy to know when 100% duty cycle will end.

[#6]

Hi honglinshi,

Is it possible if you set your 100% duty cycle with CR2 = 1?
Instead of having 0 for both CR1 and CR2 for 100% duty cycle, set CR2 is set to 1.
Then toggling of the output at the last cycle will happen and it will be correct when changing to 80% duty cycle.